From owner-freebsd-arm@freebsd.org Sat Nov 7 11:30:18 2015 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1599EA275F9 for ; Sat, 7 Nov 2015 11:30:18 +0000 (UTC) (envelope-from kostikbel@gmail.com) Received: from kib.kiev.ua (kib.kiev.ua [IPv6:2001:470:d5e7:1::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 861091770 for ; Sat, 7 Nov 2015 11:30:17 +0000 (UTC) (envelope-from kostikbel@gmail.com) Received: from tom.home (kostik@localhost [127.0.0.1]) by kib.kiev.ua (8.15.2/8.15.2) with ESMTPS id tA7BUCww084234 (version=TLSv1 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Sat, 7 Nov 2015 13:30:12 +0200 (EET) (envelope-from kostikbel@gmail.com) DKIM-Filter: OpenDKIM Filter v2.10.3 kib.kiev.ua tA7BUCww084234 Received: (from kostik@localhost) by tom.home (8.15.2/8.15.2/Submit) id tA7BUBlU084229; Sat, 7 Nov 2015 13:30:11 +0200 (EET) (envelope-from kostikbel@gmail.com) X-Authentication-Warning: tom.home: kostik set sender to kostikbel@gmail.com using -f Date: Sat, 7 Nov 2015 13:30:11 +0200 From: Konstantin Belousov To: George Abdelmalik Cc: freebsd-arm@freebsd.org Subject: Re: atomic_testandset_int seems unimplemented Message-ID: <20151107113011.GW2257@kib.kiev.ua> References: <563DA3E8.2060802@uniridge.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <563DA3E8.2060802@uniridge.com.au> User-Agent: Mutt/1.5.24 (2015-08-30) X-Spam-Status: No, score=-2.0 required=5.0 tests=ALL_TRUSTED,BAYES_00, DKIM_ADSP_CUSTOM_MED,FREEMAIL_FROM,NML_ADSP_CUSTOM_MED autolearn=no autolearn_force=no version=3.4.1 X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on tom.home X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Nov 2015 11:30:18 -0000 On Sat, Nov 07, 2015 at 06:10:32PM +1100, George Abdelmalik wrote: > Hi, > > My reading of atomic(9) implies that the atomic_testandset_* family of > functions should be present > on the arm architecture, however I don't see any evidence of it in any > of the expected locations, > ./sys/arm/include/atomic-v4.h > ./sys/arm/include/atomic-v6.h > ./sys/arm/include/atomic.h > > Is there some impediment within the architecture which doesn't make that > semantic possible or is > it just that there is no in-tree consumer yet? No consumers, apparently. testandset has somewhat rarely needed semantic, and readandclear semantic is not complimentary, to confuse the users even more. > > Any thoughts on this matter would be appreciated, or better yet a > possible implementation - sadly for > me assembly is not my strength. Below is the patch for ARMv6. I did not tested the _64 implementation, and I also doubt that we run in big endian mode for ARMv6 at all. Do you also need an implementation for ARMv5 ? diff --git a/sys/arm/include/atomic-v6.h b/sys/arm/include/atomic-v6.h index d22f7e1..9ee8043 100644 --- a/sys/arm/include/atomic-v6.h +++ b/sys/arm/include/atomic-v6.h @@ -593,6 +593,60 @@ atomic_store_rel_long(volatile u_long *p, u_long v) *p = v; } +static __inline int +atomic_testandset_32(volatile uint32_t *p, u_int v) +{ + uint32_t tmp, tmp2, res, mask; + + mask = 1u << (v & 0x1f); + tmp = tmp2 = 0; + __asm __volatile( + "1: ldrex %0, [%3] \n" + " orr %1, %0, %4 \n" + " strex %2, %1, [%3] \n" + " cmp %2, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (res), "=&r" (tmp), "=&r" (tmp2), "+&r" (p) + : "r" (mask) + : "cc", "memory"); + return ((res & mask) != 0); +} + +static __inline int +atomic_testandset_int(volatile u_int *p, u_int v) +{ + + return (atomic_testandset_32((volatile uint32_t *)p, v)); +} + +static __inline int +atomic_testandset_long(volatile u_long *p, u_int v) +{ + + return (atomic_testandset_32((volatile uint32_t *)p, v)); +} + +static __inline int +atomic_testandset_64(volatile uint64_t *p, u_int v) +{ + volatile uint32_t *p32; + + p32 = (volatile uint32_t *)p; +#if BYTE_ORDER == LITTLE_ENDIAN + if (v >= 32) { + v &= 0x1f; + p32++; + } +#else + if (v >= 32) + v &= 0x1f; + else + p32++; +#endif + return (atomic_testandset_32(p32, v)); +} + #undef ATOMIC_ACQ_REL #undef ATOMIC_ACQ_REL_LONG