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Date: Tue, 15 Apr 2008 09:46:02 +0100
From: David Malone <dwmalone@maths.tcd.ie>
To: Jeff Roberson <jroberson@jroberson.net>
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Cc: gnn@freebsd.org, Andrew Gallatin <gallatin@cs.duke.edu>,
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Subject: Re: TSC Timecounter and multi-core/SMP
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On Mon, Apr 14, 2008 at 09:51:42PM -1000, Jeff Roberson wrote:
> I think we should confirm whether this is the case with earlier opterson. 
> I have seen two processors on the same die out of sync.

This can definitely happen according to this note from AMD, which
someone posted a link to earlier in the thread:

	http://lkml.org/lkml/2005/11/4/173

it can happen when you hlt one core, but don't hlt the other on
some processors.

	David.