From owner-freebsd-arm@FreeBSD.ORG Thu Dec 19 14:29:21 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C1D936F1 for ; Thu, 19 Dec 2013 14:29:21 +0000 (UTC) Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 55E15159F for ; Thu, 19 Dec 2013 14:29:20 +0000 (UTC) Received: by mail-wi0-f169.google.com with SMTP id hn6so6636050wib.4 for ; Thu, 19 Dec 2013 06:29:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=kyuYIF+rujAOe1JgvsyjqRfSEbyh3YBifo7HCouHXnA=; b=GZ4L7HUpFMQ8jT9mDiCQrdokvtvcec3lD6EQgoUPW1pbr9ASB6+NNRLvezfES9bfxG vUq4LFzwl8+OgWZ7g/UM95YGiOi3Q3Ahcbw2dbG12rqWlgOb3H87mpJ0FQdN3+HubApP aN/ke9eyxU6QhRDFHqioGGDqL2CIe5vlCq3KOxxphw40qRip7FqhzADoN0oI+zR4jkYk 4TddJ+gN32zEvE/AzsN4qwKPgUin+CKgTAnNdLpn+yQsAAxgB+OsSPPL40u2rI1X13qb eXHkeUnmhMIYeLQMXy4UWzgCsJRC/vyvxcVKSJbsqVC6PYHQUTuvwncFQdFaqg184DJc mbmQ== X-Gm-Message-State: ALoCoQkkRQbrxe7m1zn46j/wB/DNnhqWLMj/EeLeu6xOCrayEmhfKagZ2KmWL3rEz6uKRoFyrTzF MIME-Version: 1.0 X-Received: by 10.180.205.162 with SMTP id lh2mr2482426wic.57.1387461763209; Thu, 19 Dec 2013 06:02:43 -0800 (PST) Received: by 10.216.17.73 with HTTP; Thu, 19 Dec 2013 06:02:43 -0800 (PST) In-Reply-To: <20131219131426.GA17686@ci0.org> References: <20131219131426.GA17686@ci0.org> Date: Thu, 19 Dec 2013 15:02:43 +0100 Message-ID: Subject: Re: arm SMP on Cortex-A15 From: Wojciech Macek To: Olivier Houchard Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.17 Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Dec 2013 14:29:21 -0000 Regarding 2., I would consider it as a proof of concept, or the least invasive workaround - a lot of those flushes might not be necessary. But it suggests, that there is a place in pmap where a situation of prefetching old TLB can happen. I've seen some functions where, for example, flush&pte_sync order is reversed, so this is the path that needs to be investigated to get a proper fix. Wojtek 2013/12/19 Olivier Houchard > Hi Wojciech, > > On Thu, Dec 19, 2013 at 12:41:59PM +0100, Wojciech Macek wrote: > > Hi, > > > > Finally, I'm able to run FreeBSD stable on Cortex-A15. The TLB issue > which > > was observed, was caused by an aggressive A15 feature called "L2 TLB > > prefetch". > > > > Wow that's great news ! > > > There are 4 fixes that helped: > > 0. Prerequisite, Olivier's patch for PCPU atomicity. > > Cool, I'll commit it, then. > > > 1. TEX remap - to be compliant with spec, TEX remap is used to configure > > memory as Inner Shareable > > 2. TLB flush SE - after each PTE modification and PTE_SYNC, there is no > > guarantee that newly created entry is not overlapped by old value in TLB > > cache. Do flush_SE to ensure proper mapping. > > Wow, I failed to realized we were missing so many flush. And I've read the > pmap code to find any of those many many times. Great work ! > > > > 3. During context switch, ensure that tlb flush is executed after ttb is > > changed. Clean BTB to be compliant with specs. > > > > Above patches can be found here > > > https://drive.google.com/folderview?id=0B-7yTLrPxaWteWFtWUQxVVNHVFk&usp=sharing > > > > > > None of them is 100%-ready, but should work. Any comments and/or testing > > are really appreciated. > > > > Regards, > > Olivier >