Date: Mon, 23 Apr 2012 19:44:34 +0800 From: Fengwei yin <yfw.bsd@gmail.com> To: Slawa Olhovchenkov <slw@zxy.spb.ru> Cc: jack.ren@intel.com, freebsd-threads@freebsd.org Subject: Re: About the memory barrier in BSD libc Message-ID: <CAPHpMumWu_aaZ4Sj5Athro6441Y%2B3_phbD2jxkKE-CdBf-Fd8g@mail.gmail.com> In-Reply-To: <20120423113838.GT32749@zxy.spb.ru> References: <CAPHpMu=DOGQ=TuFeYH7bH8hVwteT4Q3k67-mvoOFob6P3Y506w@mail.gmail.com> <20120423084120.GD76983@zxy.spb.ru> <CAPHpMu=kCwhf1RV_sYBDWDPL8368YTMLXge4L_g_F4AkTX1H5g@mail.gmail.com> <20120423094043.GS32749@zxy.spb.ru> <CAPHpMukLUeetSKpH2oiKJQ3ML_PFHEi6a0hK3_Ery=LX1YEd3g@mail.gmail.com> <20120423113838.GT32749@zxy.spb.ru>
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On Mon, Apr 23, 2012 at 7:38 PM, Slawa Olhovchenkov <slw@zxy.spb.ru> wrote:
> On Mon, Apr 23, 2012 at 07:26:54PM +0800, Fengwei yin wrote:
>
>> On Mon, Apr 23, 2012 at 5:40 PM, Slawa Olhovchenkov <slw@zxy.spb.ru> wro=
te:
>> > On Mon, Apr 23, 2012 at 05:32:24PM +0800, Fengwei yin wrote:
>> >
>> >> On Mon, Apr 23, 2012 at 4:41 PM, Slawa Olhovchenkov <slw@zxy.spb.ru> =
wrote:
>> >> > On Mon, Apr 23, 2012 at 02:56:03PM +0800, Fengwei yin wrote:
>> >> >
>> >> >> Hi list,
>> >> >> If this is not correct question on the list, please let me know an=
d
>> >> >> sorry for noise.
>> >> >>
>> >> >> I have a question regarding the BSD libc for SMP arch. I didn't se=
e
>> >> >> memory barrier used in libc.
>> >> >> How can we make sure it's safe on SMP arch?
>> >> >
>> >> > /usr/include/machine/atomic.h:
>> >> >
>> >> > #define mb() =A0 =A0__asm __volatile("lock; addl $0,(%%esp)" : : : =
"memory")
>> >> > #define wmb() =A0 __asm __volatile("lock; addl $0,(%%esp)" : : : "m=
emory")
>> >> > #define rmb() =A0 __asm __volatile("lock; addl $0,(%%esp)" : : : "m=
emory")
>> >> >
>> >>
>> >> Thanks for the information. But it looks no body use it in libc.
>> >
>> > I think no body in libc need memory barrier: libc don't work with
>> > peripheral, for atomic opertions used different macros.
>>
>> If we check the usage of __sinit(), it is a typical singleton pattern wh=
ich
>> needs memory barrier to make sure no potential SMP issue.
>>
>> Or did I miss something here?
>
> What architecture with cache incoherency and FreeBSD support?
I suppose it's not related with cache inchoherency (I could be wrong).
It's related
with reorder of instruction by CPU.
Here is the link talking about why need memory barrier for singleton:
http://www.oaklib.org/docs/oak/singleton.html
x86 has strict memory model and may not suffer this kind of issue. But
ARM need to
take care of it IMHO.
Regards
Yin, Fengwei
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