From owner-svn-src-all@FreeBSD.ORG Thu Mar 26 10:44:18 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id E1D514FE; Thu, 26 Mar 2015 10:44:17 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CBCF91DD; Thu, 26 Mar 2015 10:44:17 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t2QAiG2q094786; Thu, 26 Mar 2015 10:44:16 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t2QAiGt8094785; Thu, 26 Mar 2015 10:44:16 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201503261044.t2QAiGt8094785@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Thu, 26 Mar 2015 10:44:16 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r280684 - stable/10/sys/x86/iommu X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Mar 2015 10:44:18 -0000 Author: kib Date: Thu Mar 26 10:44:16 2015 New Revision: 280684 URL: https://svnweb.freebsd.org/changeset/base/280684 Log: MFC r280254: Provide definitions for all descriptors types in the DMAR invalidation queue. Modified: stable/10/sys/x86/iommu/intel_reg.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/x86/iommu/intel_reg.h ============================================================================== --- stable/10/sys/x86/iommu/intel_reg.h Thu Mar 26 10:27:39 2015 (r280683) +++ stable/10/sys/x86/iommu/intel_reg.h Thu Mar 26 10:44:16 2015 (r280684) @@ -180,7 +180,7 @@ typedef struct dmar_irte { /* IOTLB Register Offset */ #define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ #define DMAR_ECAP_PT (1 << 6) /* Pass Through */ -#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */ +#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode (x2APIC) */ #define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ #define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ #define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ @@ -320,8 +320,8 @@ typedef struct dmar_irte { #define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) /* Descriptor size */ -#define DMAR_IQ_DESCR_CTX_INV 0x1 /* Context-cache Invalidate - Descriptor */ +/* Context-cache Invalidate Descriptor */ +#define DMAR_IQ_DESCR_CTX_INV 0x1 #define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ #define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ #define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ @@ -329,7 +329,8 @@ typedef struct dmar_irte { #define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ #define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ -#define DMAR_IQ_DESCR_IOTLB_INV 0x2 /* IOTLB Invalidate Descriptor */ +/* IOTLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_IOTLB_INV 0x2 #define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ #define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ #define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ @@ -337,17 +338,31 @@ typedef struct dmar_irte { #define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ -#define DMAR_IQ_DESCR_IEC_INV 0x4 /* Invalidate Interrupt Entry Cache */ +/* Device-TLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_DTLB_INV 0x3 + +/* Invalidate Interrupt Entry Cache */ +#define DMAR_IQ_DESCR_IEC_INV 0x4 #define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ #define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ #define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ -#define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */ +/* Invalidation Wait Descriptor */ +#define DMAR_IQ_DESCR_WAIT_ID 0x5 #define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ #define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ #define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ #define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ +/* Extended IOTLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_EIOTLB_INV 0x6 + +/* PASID-Cache Invalidate Descriptor */ +#define DMAR_IQ_DESCR_PASIDC_INV 0x7 + +/* Extended Device-TLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_EDTLB_INV 0x8 + /* Invalidation Queue Head register */ #define DMAR_IQH_REG 0x80 #define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */