From owner-svn-src-head@FreeBSD.ORG Mon Feb 24 03:47:39 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D6389CEC; Mon, 24 Feb 2014 03:47:39 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id C21AF19F1; Mon, 24 Feb 2014 03:47:39 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s1O3ldkx093537; Mon, 24 Feb 2014 03:47:39 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s1O3ldtt093536; Mon, 24 Feb 2014 03:47:39 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201402240347.s1O3ldtt093536@svn.freebsd.org> From: Ian Lepore Date: Mon, 24 Feb 2014 03:47:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262426 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Feb 2014 03:47:39 -0000 Author: ian Date: Mon Feb 24 03:47:39 2014 New Revision: 262426 URL: http://svnweb.freebsd.org/changeset/base/262426 Log: Invalidate caches immediately upon entry to init_secondary(). Also set the Bufferable bit in the PDE entries of the secondary processor startup pagetables. The caches really need to be invalidated even earlier than this, but this is a big step in the right direction. The invalidate needs to happen before the MMU is enabled, which means it has to be called from asm code that's running with physical addressing. Fixing that will be handled in a future change. Modified: head/sys/arm/arm/mp_machdep.c Modified: head/sys/arm/arm/mp_machdep.c ============================================================================== --- head/sys/arm/arm/mp_machdep.c Mon Feb 24 02:47:47 2014 (r262425) +++ head/sys/arm/arm/mp_machdep.c Mon Feb 24 03:47:39 2014 (r262426) @@ -128,10 +128,10 @@ cpu_mp_start(void) bzero((void *)temp_pagetable_va, L1_TABLE_SIZE); for (addr = arm_physmem_kernaddr; addr <= addr_end; addr += L1_S_SIZE) { ((int *)(temp_pagetable_va))[addr >> L1_S_SHIFT] = - L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; + L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; ((int *)(temp_pagetable_va))[(addr - arm_physmem_kernaddr + KERNVIRTADDR) >> L1_S_SHIFT] = - L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; + L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; } #if defined(CPU_MV_PJ4B) @@ -173,6 +173,8 @@ init_secondary(int cpu) uint32_t loop_counter; int start = 0, end = 0; + cpu_idcache_inv_all(); + cpu_setup(NULL); setttb(pmap_pa); cpu_tlb_flushID();