Date: Fri, 15 Dec 2006 08:47:18 -0800 (PST) From: Simon Roberts <thorpflyer@yahoo.com> To: freebsd-hackers@freebsd.org Subject: Re: "Syncing cpus" on a multi-cpu, dual core system Message-ID: <20061215164718.60395.qmail@web60917.mail.yahoo.com>
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=0A----- Original Message ----=0A> On a computational chemistry list I subs= cribe to there is a=0A> current thread about multi-cpu systems needing to h= ave the cpu=0A> frequencies synced (this is in a Linux context). This is= =0A> evidently not just having the cpus running at nominally the same=0A> f= requency but something else in addition. A posting in the thread=0A> said = variations less than 0.1% were not problematic. However, the=0A> poster sa= id it was an issue in a dual cpu, dual core system he had=0A> set up.=0A> = =0A> My questions are:=0A> 1. Is this real or an urban legend?=0A=0AIf CPUs= use the same FSB (as is the case with dual-core chip), they are=0Aalready = in sync. Right? For system that use multiple FSB clocks [like=0Adual-(dualc= ore-CPU) systems], it might be possible to vary the clocks=0A(as much as th= e manufacturer allows without hw modifications: e.g.,=0ASpeedStep, or somet= hing similar).=0A=0AWhy someone would want to have CPUs running at precisel= y the same=0Afrequency is beyond my imagination.=0A=0A---------------------= -----------------------=0A=0AMy dual core system does speedstep the two CPU= s independently, it's clearly visible when running the speed monitor applet= s. I guess if only one thread is busy, only one CPU needs to work hard.=0A= =0AAs to why it would matter that they be in sync? My imagination runs to t= hese two possibilities: 1) someone is writing multi-threaded software but d= oesn't really know how to do this correctly. 2) someone is writing ultra-hi= gh performance multi-threaded software that requires two threads on the two= CPUs to be able to run in a way that doesn't risk data corruption, but nee= ds to be able to do it without slowing down to check monitors/semaphores/ot= her-threadsafety-devices. To address this, they've counted CPU cycles and a= re running a producer and consumer type scenario in such a way that the thr= eads are perfectly out of phase with one another, so as to ensure that read= s by one are not mixed in with writes by the other. I guess option 2 would = be kinda legitimate, but I suspect actually a special case of 1 anyway--mai= nly because I find it hard to believe it has a snowball's chance in hell of= working on systems that have pipelines, instruction look-ahead, etc. Might= have worked on a dual 6502 based system when you knew exactly how long an = instruction would take, and it always took that long :)=0A=0ABottom line; I= 'm inclined to the urban-legend classification.=0A=0A$0.02=0ASimon=0A=0A=0A= =0A=0A=0A__________________________________________________=0ADo You Yahoo!= ?=0ATired of spam? Yahoo! Mail has the best spam protection around =0Ahttp= ://mail.yahoo.com
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