Date: Sat, 10 Jan 2015 02:29:45 +0000 (UTC) From: Benjamin Kaduk <bjk@FreeBSD.org> To: doc-committers@freebsd.org, svn-doc-all@freebsd.org, svn-doc-head@freebsd.org Subject: svn commit: r46186 - head/en_US.ISO8859-1/htdocs/news/status Message-ID: <201501100229.t0A2TjTu036590@svn.freebsd.org>
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Author: bjk Date: Sat Jan 10 02:29:44 2015 New Revision: 46186 URL: https://svnweb.freebsd.org/changeset/doc/46186 Log: Add PCI SR-IOV report Approved by: hrs (mentor, blanket) Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2014-10-2014-12.xml Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2014-10-2014-12.xml ============================================================================== --- head/en_US.ISO8859-1/htdocs/news/status/report-2014-10-2014-12.xml Sat Jan 10 01:18:47 2015 (r46185) +++ head/en_US.ISO8859-1/htdocs/news/status/report-2014-10-2014-12.xml Sat Jan 10 02:29:44 2015 (r46186) @@ -2051,4 +2051,53 @@ </help> </project> + <project cat='kern'> + <title>PCI SR-IOV Infrastructure</title> + + <contact> + <person> + <name> + <given>Ryan</given> + <common>Stone</common> + </name> + <email>rstone@FreeBSD.org</email> + </person> + </contact> + + <links> + <url href="https://github.com/rysto32/freebsd/commits/iov_ixl" /> + </links> + + <body> + <p>PCI Single Root I/O Virtualization (SR-IOV) is an optional part + of the PCIe standard that provides hardware acceleration for the + virtualization of PCIe devices. When SR-IOV is in use, a function in a + PCI device (known as a Physical Function, or PF) will present multiple + Virtual PCI Functions (VF) on the PCI bus. These VFs are fully + independent PCI devices that have access to the resources of the PF. + For example, on a network interface card, VFs could transmit and + receive packets independent of the PF.</p> + + <p>The most obvious use case for SR-IOV is virtualization. A + hypervisor like bhyve could instantiate a VF for every VM and use PCI + passthrough to assign the VFs to the VMs. This would allow multiple + VMs to share access to the PCI device without having to do any + expensive communication with the hypervisor, greatly increasing + performance of performing I/O from a VM.</p> + + <p>Work on the core PCI infrastructure is complete and undergoing + review. Currently it is planned to commit the PCI infrastructure to + head by the end of January.</p> + + <p>In additional to the PCI infrastructure, individual PCI drivers + must be extended to implement SR-IOV. An SR-IOV implementation is in + progress for the ixl(4) driver, which supports the Intel XL710 family + of 40G and 10G NICs. Currently it is planned to have this in review + by the end of January. An implementation for ixgbe(4) is also in + progress, but there is no timeline for completion.</p> + </body> + + <sponsor>Sandvine Inc.</sponsor> + </project> + </report>
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