From nobody Fri Mar 11 11:31:29 2022 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 2602E19FAEDF; Fri, 11 Mar 2022 11:31:30 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4KFP020GKdz4vW2; Fri, 11 Mar 2022 11:31:30 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1646998290; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YcuAv1/kHwDabNuLyLYnUhkpZRFjemRZiWWGUgFkiYo=; b=jaLaUWDEh/DdKPPbRLrdAQCKpqGCrp7/fsjBvRDxq7ce7taK1/mM7FWTdhcQsHEGAa0s+2 pUUEXi03wQP+zi8Gc8J0V9LHRrdmD03HQoMqbog40NZ13fxmn1hu1TXd9GaLnbP6FiHc3Y /+4kBM38uf2mIlJbTVS09Vx8jWNBM7iYhVc4xc+gT5sMS0secnvUqK7jYlacgituGhUtck Z/5JJyQedKacasvdhQYvp4nWfe08qefBbEqKpLTYJCicWpciJ+LRIcUHv34gnkVo2vPYq4 Ic1HfR0qzsRQp9cT+cfzzC8Ums9Wf8Xt1xFao+KGrMclBK4ZCHK72UXae/6wrw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id DD9F518A06; Fri, 11 Mar 2022 11:31:29 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 22BBVTYh076659; Fri, 11 Mar 2022 11:31:29 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 22BBVTEN076658; Fri, 11 Mar 2022 11:31:29 GMT (envelope-from git) Date: Fri, 11 Mar 2022 11:31:29 GMT Message-Id: <202203111131.22BBVTEN076658@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: a1b4e4fa9a2f - main - Correct the location of the arm64 PMCR register List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: a1b4e4fa9a2f8bef9adff9e93cc5152e46a2ff4e Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1646998290; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YcuAv1/kHwDabNuLyLYnUhkpZRFjemRZiWWGUgFkiYo=; b=F2/cp1njt5pzuVfMHltefVZyofkA1MJ89pzJsMeetF1EUwWQArj2mI78JzLGEEBJGT5rof THqYlvuanJD+aPTrd8i2iRQNKSJDcTHFo1zwLII7zwelNm8n81asJOK0CY8nHrZAn1C6K9 i1aT9ChYsnmKsh/XQRsj4UnNIL8xs0YHezRqQYvrxTX00Vtotx6RWS/jWyegLPAX13YpxY QYnTHv7JH7caqmmSocu2dGlc0u8jdjOOmbatq2UfcRkxC7YVwIG3UvJjiKzLkHDRuZ/nag ABxXpAjJS1N/pMX2C4O81znzCUX4PON49UFGpcg8QpwQtTDQZ4AKWBz1uMQCMQ== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1646998290; a=rsa-sha256; cv=none; b=kYV5u2mqPHkkh2ZkvDN1F4+eX+vQlQkRQXAWzhXPVa6r4YEPrZ0i/dbXUgZEVKGEcZIVh5 srM8F+uiIGKInaQNxTf/JXqobsUMN7inpN+ZfIZHPsQyVeSOCOwd9AWElwyt9y5XFUVGyp X79KtJSylgYRU1hMq2383OE+kEEWOdgCZkal6hl+MCBEaj7oEew+04OveS00mYnjCq6Wgh 7KwW3DHV/RzPIaPTqSSLs1d5/HuMqOVPbUT1v4qu4OqWpSOW42rtbojvNWD+Z4GYB91fqA uhO8IHWP3RfcqKxMP5ZXfBigfNBiuQKqlLTsbeJ51ebBIKHM6S8CxDEFGig47A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=a1b4e4fa9a2f8bef9adff9e93cc5152e46a2ff4e commit a1b4e4fa9a2f8bef9adff9e93cc5152e46a2ff4e Author: Andrew Turner AuthorDate: 2022-03-11 10:56:42 +0000 Commit: Andrew Turner CommitDate: 2022-03-11 11:21:09 +0000 Correct the location of the arm64 PMCR register This was one of the last registers to not be in alphabetical order in armreg.h. Fix this to make it easier to find. Sponsored by: Innovate UK --- sys/arm64/include/armreg.h | 55 +++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 4f9b60461a2f..86e43190e002 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -1111,6 +1111,33 @@ #define PMBSR_EC_SHIFT 26 #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) +/* PMCR_EL0 - Perfomance Monitoring Counters */ +#define PMCR_E (1 << 0) /* Enable all counters */ +#define PMCR_P (1 << 1) /* Reset all counters */ +#define PMCR_C (1 << 2) /* Clock counter reset */ +#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ +#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ +#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define PMCR_LC (1 << 6) /* Long cycle count enable */ +#define PMCR_IMP_SHIFT 24 /* Implementer code */ +#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) +#define PMCR_IMP_ARM 0x41 +#define PMCR_IDCODE_SHIFT 16 /* Identification code */ +#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) +#define PMCR_IDCODE_CORTEX_A57 0x01 +#define PMCR_IDCODE_CORTEX_A72 0x02 +#define PMCR_IDCODE_CORTEX_A53 0x03 +#define PMCR_IDCODE_CORTEX_A73 0x04 +#define PMCR_IDCODE_CORTEX_A35 0x0a +#define PMCR_IDCODE_CORTEX_A76 0x0b +#define PMCR_IDCODE_NEOVERSE_N1 0x0c +#define PMCR_IDCODE_CORTEX_A77 0x10 +#define PMCR_IDCODE_CORTEX_A55 0x45 +#define PMCR_IDCODE_NEOVERSE_E1 0x46 +#define PMCR_IDCODE_CORTEX_A75 0x4a +#define PMCR_N_SHIFT 11 /* Number of counters implemented */ +#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) + /* PMSCR_EL1 */ #define PMSCR_EL1 MRS_REG(PMSCR_EL1) #define PMSCR_EL1_op0 0x3 @@ -1436,32 +1463,4 @@ #define TTBR_CnP_SHIFT 0 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) - -/* Perfomance Monitoring Counters */ -#define PMCR_E (1 << 0) /* Enable all counters */ -#define PMCR_P (1 << 1) /* Reset all counters */ -#define PMCR_C (1 << 2) /* Clock counter reset */ -#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ -#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ -#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define PMCR_LC (1 << 6) /* Long cycle count enable */ -#define PMCR_IMP_SHIFT 24 /* Implementer code */ -#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) -#define PMCR_IMP_ARM 0x41 -#define PMCR_IDCODE_SHIFT 16 /* Identification code */ -#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) -#define PMCR_IDCODE_CORTEX_A57 0x01 -#define PMCR_IDCODE_CORTEX_A72 0x02 -#define PMCR_IDCODE_CORTEX_A53 0x03 -#define PMCR_IDCODE_CORTEX_A73 0x04 -#define PMCR_IDCODE_CORTEX_A35 0x0a -#define PMCR_IDCODE_CORTEX_A76 0x0b -#define PMCR_IDCODE_NEOVERSE_N1 0x0c -#define PMCR_IDCODE_CORTEX_A77 0x10 -#define PMCR_IDCODE_CORTEX_A55 0x45 -#define PMCR_IDCODE_NEOVERSE_E1 0x46 -#define PMCR_IDCODE_CORTEX_A75 0x4a -#define PMCR_N_SHIFT 11 /* Number of counters implemented */ -#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) - #endif /* !_MACHINE_ARMREG_H_ */