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To: rb@gid.co.uk
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Subject: Cyrix DX2/4
In-Reply-To: Your message of "Thu, 24 Apr 1997 08:31:02 +0100"
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Date: Thu, 24 Apr 1997 17:58:27 +0900
From: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
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I don't forget PR/3292 :-), and I'm looking for information of Cyrix
486S/DX series CPUs.

> The root of this problem appears to be that Cyrix 486 DX DX2 and DX4 (and
> some equivalent TI-branded parts) are correctly identified, but are
> misclassified as CPU_486DLC where they should be just plain CPU_486. The
> following patch fixes the problem:

Cyrix/Ti/IBM 486DX2/DX4 have special registers (CCR1, CCR2, CCR3 and
SMAR), but they don't have CCR0 (from BIOS Writer's Guide).  If
neither CYRIX_CACHE_WORKS nor CYRIX_CACHE_REALLY_WORKS is not set,
only CCR0 is modified.  This operation should not have any effect on
DX2 / DX4 because they doesn't have CCR0.  Did you get any problem
with initcpu.c revision 1.3?

If problem still remains, I would summit following idea:

init_486dlc()
{
	u_long	eflags;
	u_char	ccr0;

	if ((cyrix_did & 0x00f0) == 0x00) {
		/* 486 like CPU with 386 like bus. */
		...  /* same as revsion 1.3 */
	} else {
		/* 486 like CPU with 486 like bus. */
		/* Should I support write-back cache? */
	}
}

I consider that `CPU_486' means Intel's 486, which does not have any
special registers, and `CPU_486DLC' means Cyrix's 486, which has
special registers.


----
KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
Dept. Earth Planet. Sci., Nagoya Univ.,  Nagoya, 464-01, Japan
PGP public key: finger kato@eclogite.eps.nagoya-u.ac.jp
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