From owner-svn-src-all@freebsd.org Thu May 16 16:34:13 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1DC04159DE66; Thu, 16 May 2019 16:34:13 +0000 (UTC) (envelope-from hselasky@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id B61BC8A80C; Thu, 16 May 2019 16:34:12 +0000 (UTC) (envelope-from hselasky@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8FEC423718; Thu, 16 May 2019 16:34:12 +0000 (UTC) (envelope-from hselasky@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x4GGYCur076231; Thu, 16 May 2019 16:34:12 GMT (envelope-from hselasky@FreeBSD.org) Received: (from hselasky@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x4GGYCFn076229; Thu, 16 May 2019 16:34:12 GMT (envelope-from hselasky@FreeBSD.org) Message-Id: <201905161634.x4GGYCFn076229@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: hselasky set sender to hselasky@FreeBSD.org using -f From: Hans Petter Selasky Date: Thu, 16 May 2019 16:34:12 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r347775 - stable/12/sys/dev/mlx5/mlx5_en X-SVN-Group: stable-12 X-SVN-Commit-Author: hselasky X-SVN-Commit-Paths: stable/12/sys/dev/mlx5/mlx5_en X-SVN-Commit-Revision: 347775 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: B61BC8A80C X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.98 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.998,0]; NEURAL_HAM_SHORT(-0.98)[-0.979,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 May 2019 16:34:13 -0000 Author: hselasky Date: Thu May 16 16:34:11 2019 New Revision: 347775 URL: https://svnweb.freebsd.org/changeset/base/347775 Log: MFC r347310: Expose per-lane counters before correction mechanism in mlx5en(4). Sponsored by: Mellanox Technologies Modified: stable/12/sys/dev/mlx5/mlx5_en/en.h stable/12/sys/dev/mlx5/mlx5_en/mlx5_en_main.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/dev/mlx5/mlx5_en/en.h ============================================================================== --- stable/12/sys/dev/mlx5/mlx5_en/en.h Thu May 16 16:33:35 2019 (r347774) +++ stable/12/sys/dev/mlx5/mlx5_en/en.h Thu May 16 16:34:11 2019 (r347775) @@ -280,6 +280,24 @@ struct mlx5e_vport_stats { m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") +#define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ + m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ + "Time since last clear in milliseconds") \ + m(+1, u64, phy_received_bits, "phy_received_bits", \ + "Total amount of traffic received in bits before error correction") \ + m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ + "Total number of symbol errors before error correction") \ + m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ + "Total number of corrected bits ") \ + m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ + "Total number of corrected bits for lane 0") \ + m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ + "Total number of corrected bits for lane 1") \ + m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ + "Total number of corrected bits for lane 2") \ + m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ + "Total number of corrected bits for lane 3") + #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ m(+1, u64, time_since_last_clear, "time_since_last_clear", \ "Time since the last counters clear event (msec)") \ @@ -522,6 +540,7 @@ struct mlx5e_vport_stats { MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ + MLX5E_PPORT_STATISTICAL_DEBUG(m) \ MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ @@ -544,6 +563,8 @@ struct mlx5e_vport_stats { (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) +#define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ + (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) #define MLX5E_PORT_STATS_DEBUG_NUM \ (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) Modified: stable/12/sys/dev/mlx5/mlx5_en/mlx5_en_main.c ============================================================================== --- stable/12/sys/dev/mlx5/mlx5_en/mlx5_en_main.c Thu May 16 16:33:35 2019 (r347774) +++ stable/12/sys/dev/mlx5/mlx5_en/mlx5_en_main.c Thu May 16 16:34:11 2019 (r347775) @@ -769,6 +769,18 @@ mlx5e_update_pport_counters(struct mlx5e_priv *priv) for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) s_debug->arg[y] = be64toh(ptr[x]); + /* read Extended Statistical Group */ + if (MLX5_CAP_GEN(mdev, pcam_reg) && + MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && + MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { + /* read Extended Statistical counter group using predefined counter layout */ + MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); + + for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) + s_debug->arg[y] = be64toh(ptr[x]); + } + /* read PCIE counters */ mlx5e_update_pcie_counters(priv);