From owner-svn-src-all@FreeBSD.ORG Sun Apr 28 00:46:00 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 0B1A61BA; Sun, 28 Apr 2013 00:46:00 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id EEE0A10E8; Sun, 28 Apr 2013 00:45:59 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.6/8.14.6) with ESMTP id r3S0jxlq041974; Sun, 28 Apr 2013 00:45:59 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.6/8.14.5/Submit) id r3S0jxjO041967; Sun, 28 Apr 2013 00:45:59 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201304280045.r3S0jxjO041967@svn.freebsd.org> From: Adrian Chadd Date: Sun, 28 Apr 2013 00:45:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r250003 - in vendor/qcamain_open_hal: . dist dist/hal dist/hal/ar9300 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Apr 2013 00:46:00 -0000 Author: adrian Date: Sun Apr 28 00:45:58 2013 New Revision: 250003 URL: http://svnweb.freebsd.org/changeset/base/250003 Log: Initial import of the QCA qcamain_open_hal repository. Source: https://github.com/qca/qcamain_open_hal_public Revision: 60390a9f9ac6a20db168fbbc01a4ad4e01c395ce Thankyou to QCA for this release. Added: vendor/qcamain_open_hal/ vendor/qcamain_open_hal/dist/ vendor/qcamain_open_hal/dist/LICENCE.TXT vendor/qcamain_open_hal/dist/NOTICE.TXT vendor/qcamain_open_hal/dist/README vendor/qcamain_open_hal/dist/hal/ vendor/qcamain_open_hal/dist/hal/ar9300/ vendor/qcamain_open_hal/dist/hal/ar9300/ar9300.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_aic.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_ani.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_aphrodite10.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_attach.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_beacon.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_eeprom.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_gpio.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_interrupts.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_jupiter10.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_jupiter20.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_keycache.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_mci.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_misc.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_osprey22.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_osprey22_scoemu.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_paprd.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_phy.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_power.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_radar.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_radio.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_raw_adc_capture.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_recv.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_recv_ds.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_reset.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_rtt.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_sim.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_sim.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_spectral.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_timer.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_tx99_tgt.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_txbf.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_txbf.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_txbf_cal.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_xmit.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300_xmit_ds.c vendor/qcamain_open_hal/dist/hal/ar9300/ar9300desc.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300eep.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300paprd.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300phy.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300radar.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300reg.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_ap121.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_aphrodite.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_cus157.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_generic.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_hb112.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_hb116.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_osprey_k31.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_wasp_2.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_wasp_k31.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_xb112.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9300template_xb113.h vendor/qcamain_open_hal/dist/hal/ar9300/ar9330_11.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9330_12.ini (contents, props changed) vendor/qcamain_open_hal/dist/hal/ar9300/ar9340.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9485.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9485_1_1.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar955x.ini vendor/qcamain_open_hal/dist/hal/ar9300/ar9580.ini vendor/qcamain_open_hal/dist/hal/ar9300/eeprom.diff vendor/qcamain_open_hal/dist/hal/ar9300/osprey_reg_map.h vendor/qcamain_open_hal/dist/hal/ar9300/osprey_reg_map_macro.h vendor/qcamain_open_hal/dist/hal/ar9300/poseidon_reg_map_macro.h vendor/qcamain_open_hal/dist/hal/ar9300/scorpion_reg_map.h vendor/qcamain_open_hal/dist/hal/ar9300/scorpion_reg_map_macro.h vendor/qcamain_open_hal/dist/hal/ar9300/sources vendor/qcamain_open_hal/dist/hal/ar9300/wasp_reg_map.h Added: vendor/qcamain_open_hal/dist/LICENCE.TXT ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/qcamain_open_hal/dist/LICENCE.TXT Sun Apr 28 00:45:58 2013 (r250003) @@ -0,0 +1,13 @@ +Copyright (c) 2013 Qualcomm Atheros, Inc. + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH +REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, +INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM +LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +PERFORMANCE OF THIS SOFTWARE. Added: vendor/qcamain_open_hal/dist/NOTICE.TXT ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/qcamain_open_hal/dist/NOTICE.TXT Sun Apr 28 00:45:58 2013 (r250003) @@ -0,0 +1,72 @@ +This NOTICE.TXT file contains certain notices of software components included +with the software that QUALCOMM ATHEROS Incorporated ('Qualcomm Atheros') is +required to provide you. Notwithstanding anything in the notices in this file, +your use of these software components together with the Qualcomm Atheros +software (Qualcomm Atheros software hereinafter referred to as 'Software') is +subject to the terms of your license from Qualcomm Atheros. Compliance with +all copyright laws and software license agreements included in the notice +section of this file are the responsibility of the user. Except as may be +granted by separate express written agreement, this file provides no license +to any Qualcomm Atheros patents, trademarks, copyrights, or other intellectual +property. + +Copyright (c) 2013 QUALCOMM ATHEROS Incorporated. All rights reserved. + +QUALCOMM ATHEROS® is a registered trademark and registered service mark of +QUALCOMM ATHEROS Incorporated. All other trademarks and service marks are +the property of their respective owners. + +NOTICES: + +/* + * Copyright (c) 2005-2012 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * Copyright (c) 2008-2010, Atheros Communications Inc. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + */ Added: vendor/qcamain_open_hal/dist/README ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/qcamain_open_hal/dist/README Sun Apr 28 00:45:58 2013 (r250003) @@ -0,0 +1,23 @@ +This is a public version of the AR9300 HAL, suitable for open source +development. + + +What is this? +------------- + +This is a public version of the QCA mainline (10.x) development HAL. +It has a few notable changes: + +* The boolean types have been converted back to the HAL types + (HAL_BOOL, AH_TRUE / AH_FALSE) to aid integration into the existing + open source Atheros HAL drivers; + +* Some features have been removed from this HAL. + +However, this is essentially the same HAL which is used in QCA development +and forms the basis for public releases from the 10.x mainline. + +Subsequent HAL releases will be committed on top of this release in order +to provide developers with a simple change history they can use when +doing branch merging. + Added: vendor/qcamain_open_hal/dist/hal/ar9300/ar9300.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/qcamain_open_hal/dist/hal/ar9300/ar9300.h Sun Apr 28 00:45:58 2013 (r250003) @@ -0,0 +1,1641 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ATH_AR9300_H_ +#define _ATH_AR9300_H_ + +#include "ah_internal.h" +#include "ah_eeprom.h" +#include "ah_devid.h" +#include "ar9300eep.h" /* For Eeprom definitions */ +#include "asf_amem.h" + + +#define AR9300_MAGIC 0x19741014 + + +/* MAC register values */ + +#define INIT_CONFIG_STATUS 0x00000000 +#define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ +#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ + +/* + * Various fifo fill before Tx start, in 64-byte units + * i.e. put the frame in the air while still DMAing + */ +#define MIN_TX_FIFO_THRESHOLD 0x1 +#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) +#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD + + #define CHANSEL_DIV 15 + #define FCLK 40 + +#define COEFF ((FCLK * 5) / 2) +#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) +#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) +#define CHANSEL_5G_DOT5MHZ 2188 + +/* + * Receive Queue Fifo depth. + */ +enum RX_FIFO_DEPTH { + HAL_HP_RXFIFO_DEPTH = 16, + HAL_LP_RXFIFO_DEPTH = 128, +}; + +/* + * Gain support. + */ +#define NUM_CORNER_FIX_BITS_2133 7 +#define CCK_OFDM_GAIN_DELTA 15 + +enum GAIN_PARAMS { + GP_TXCLIP, + GP_PD90, + GP_PD84, + GP_GSEL +}; + +enum GAIN_PARAMS_2133 { + GP_MIXGAIN_OVR, + GP_PWD_138, + GP_PWD_137, + GP_PWD_136, + GP_PWD_132, + GP_PWD_131, + GP_PWD_130, +}; + +enum { + HAL_RESET_POWER_ON, + HAL_RESET_WARM, + HAL_RESET_COLD, +}; + +typedef struct _gain_opt_step { + int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; + int32_t stepGain; + int8_t stepName[16]; +} GAIN_OPTIMIZATION_STEP; + +typedef struct { + u_int32_t numStepsInLadder; + u_int32_t defaultStepNum; + GAIN_OPTIMIZATION_STEP optStep[10]; +} GAIN_OPTIMIZATION_LADDER; + +typedef struct { + u_int32_t currStepNum; + u_int32_t currGain; + u_int32_t targetGain; + u_int32_t loTrig; + u_int32_t hiTrig; + u_int32_t gainFCorrection; + u_int32_t active; + GAIN_OPTIMIZATION_STEP *curr_step; +} GAIN_VALUES; + +typedef struct { + u_int16_t synth_center; + u_int16_t ctl_center; + u_int16_t ext_center; +} CHAN_CENTERS; + +/* RF HAL structures */ +typedef struct rf_hal_funcs { + HAL_BOOL (*set_channel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); + HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, HAL_CHANNEL *chans, + u_int32_t nchancs); +} RF_HAL_FUNCS; + +struct ar9300_ani_default { + u_int16_t m1_thresh_low; + u_int16_t m2_thresh_low; + u_int16_t m1_thresh; + u_int16_t m2_thresh; + u_int16_t m2_count_thr; + u_int16_t m2_count_thr_low; + u_int16_t m1_thresh_low_ext; + u_int16_t m2_thresh_low_ext; + u_int16_t m1_thresh_ext; + u_int16_t m2_thresh_ext; + u_int16_t firstep; + u_int16_t firstep_low; + u_int16_t cycpwr_thr1; + u_int16_t cycpwr_thr1_ext; +}; + +/* + * Per-channel ANI state private to the driver. + */ +struct ar9300_ani_state { + HAL_CHANNEL c; + HAL_BOOL must_restore; + HAL_BOOL ofdms_turn; + u_int8_t ofdm_noise_immunity_level; + u_int8_t cck_noise_immunity_level; + u_int8_t spur_immunity_level; + u_int8_t firstep_level; + u_int8_t ofdm_weak_sig_detect_off; + u_int8_t mrc_cck_off; + + /* Thresholds */ + u_int32_t listen_time; + u_int32_t ofdm_trig_high; + u_int32_t ofdm_trig_low; + int32_t cck_trig_high; + int32_t cck_trig_low; + int32_t rssi_thr_low; + int32_t rssi_thr_high; + + int32_t rssi; /* The current RSSI */ + u_int32_t tx_frame_count; /* Last tx_frame_count */ + u_int32_t rx_frame_count; /* Last rx Frame count */ + u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ + u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ + u_int32_t cck_phy_err_count; /* CCK err count since last reset */ + + struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ + HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ +}; + +#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ + +#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ + +#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ +#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ +#define HAL_AR_EN 0x40000000 /* AR detect is capable */ + +#define DO_ANI(ah) \ + ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) + +struct ar9300_stats { + u_int32_t ast_ani_niup; /* ANI increased noise immunity */ + u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ + u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ + u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ + u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ + u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ + u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ + u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ + u_int32_t ast_ani_stepup; /* ANI increased first step level */ + u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ + u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ + u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ + u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ + u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ + u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ + HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ + HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ +}; + +struct ar9300_rad_reader { + u_int16_t rd_index; + u_int16_t rd_expSeq; + u_int32_t rd_resetVal; + u_int8_t rd_start; +}; + +struct ar9300_rad_writer { + u_int16_t wr_index; + u_int16_t wr_seq; +}; + +struct ar9300_radar_event { + u_int32_t re_ts; /* 32 bit time stamp */ + u_int8_t re_rssi; /* rssi of radar event */ + u_int8_t re_dur; /* duration of radar pulse */ + u_int8_t re_chanIndex; /* Channel of event */ +}; + +struct ar9300_radar_q_elem { + u_int32_t rq_seqNum; + u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ + struct ar9300_radar_event rq_event; /* Radar event */ +}; + +struct ar9300_radar_q_info { + u_int16_t ri_qsize; /* q size */ + u_int16_t ri_seqSize; /* Size of sequence ring */ + struct ar9300_rad_reader ri_reader; /* State for the q reader */ + struct ar9300_rad_writer ri_writer; /* state for the q writer */ +}; + +#define HAL_MAX_ACK_RADAR_DUR 511 +#define HAL_MAX_NUM_PEAKS 3 +#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ +#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ +#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ +#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ +#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ + +struct ar9300_ar_state { + u_int16_t ar_prev_time_stamp; + u_int32_t ar_prev_width; + u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; + u_int32_t ar_ack_sum; + u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; + u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ + u_int32_t ar_par_threshold; /* Thresh to determine peak */ + u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ +}; + +struct ar9300_radar_state { + HAL_CHANNEL_INTERNAL *rs_chan; /* Channel info */ + u_int8_t rs_chan_index; /* Channel index in radar structure */ + u_int32_t rs_num_radar_events; /* Number of radar events */ + int32_t rs_firpwr; /* Thresh to check radar sig is gone */ + u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ + u_int32_t rs_height; /* Thresh for pulse height (dB)*/ + u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ + u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ +}; +typedef struct { + u_int8_t uc_receiver_errors; + u_int8_t uc_bad_tlp_errors; + u_int8_t uc_bad_dllp_errors; + u_int8_t uc_replay_timeout_errors; + u_int8_t uc_replay_number_rollover_errors; +} ar_pcie_error_moniter_counters; + +#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ +#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ +#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ +#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ +#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ +#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ + +/* + * For Kite and later chipsets, the following bits are not being programmed in EEPROM + * and so need to be enabled always. + * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 + * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 + */ +#define AR9300_RDEXT_DEFAULT 0x1F + +#define AR9300_MAX_CHAINS 3 +#define AR9300_NUM_CHAINS(chainmask) \ + (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) +#define AR9300_CHAIN0_MASK 0x1 +#define AR9300_CHAIN1_MASK 0x2 +#define AR9300_CHAIN2_MASK 0x4 + +/* Support for multiple INIs */ +struct ar9300_ini_array { + u_int32_t *ia_array; + u_int32_t ia_rows; + u_int32_t ia_columns; +}; +#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ + (iniarray)->ia_array = (u_int32_t *)(array); \ + (iniarray)->ia_rows = (rows); \ + (iniarray)->ia_columns = (columns); \ +} while (0) +#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) + +#define INIT_CAL(_perCal) \ + (_perCal)->cal_state = CAL_WAITING; \ + (_perCal)->cal_next = AH_NULL; + +#define INSERT_CAL(_ahp, _perCal) \ +do { \ + if ((_ahp)->ah_cal_list_last == AH_NULL) { \ + (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ + ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ + } else { \ + ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ + (_ahp)->ah_cal_list_last = (_perCal); \ + (_perCal)->cal_next = (_ahp)->ah_cal_list; \ + } \ +} while (0) + +typedef enum cal_types { + IQ_MISMATCH_CAL = 0x1, + TEMP_COMP_CAL = 0x2, +} HAL_CAL_TYPES; + +typedef enum cal_state { + CAL_INACTIVE, + CAL_WAITING, + CAL_RUNNING, + CAL_DONE +} HAL_CAL_STATE; /* Calibrate state */ + +#define MIN_CAL_SAMPLES 1 +#define MAX_CAL_SAMPLES 64 +#define INIT_LOG_COUNT 5 +#define PER_MIN_LOG_COUNT 2 +#define PER_MAX_LOG_COUNT 10 + +#define AR9300_NUM_BT_WEIGHTS 4 +#define AR9300_NUM_WLAN_WEIGHTS 4 + +/* Per Calibration data structure */ +typedef struct per_cal_data { + HAL_CAL_TYPES cal_type; // Type of calibration + u_int32_t cal_num_samples; // Number of SW samples to collect + u_int32_t cal_count_max; // Number of HW samples to collect + void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func + void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func +} HAL_PERCAL_DATA; + +/* List structure for calibration data */ +typedef struct cal_list { + const HAL_PERCAL_DATA *cal_data; + HAL_CAL_STATE cal_state; + struct cal_list *cal_next; +} HAL_CAL_LIST; + +#define AR9300_NUM_CAL_TYPES 2 +#define AR9300_PAPRD_TABLE_SZ 24 +#define AR9300_PAPRD_GAIN_TABLE_SZ 32 +#define AR9382_MAX_GPIO_PIN_NUM (16) +#define AR9382_GPIO_PIN_8_RESERVED (8) +#define AR9382_GPIO_9_INPUT_ONLY (9) +#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) +#define AR9382_GPIO_PIN_11_RESERVED (11) +#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) + +/* Paprd tx power adjust data structure */ +struct ar9300_paprd_pwr_adjust { + u_int32_t target_rate; // rate index + u_int32_t reg_addr; // register offset + u_int32_t reg_mask; // mask of register + u_int32_t reg_mask_offset; // mask offset of register + u_int32_t sub_db; // offset value unit of dB +}; + +#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ +struct ath_hal_9300 { + struct ath_hal_private_tables ah_priv; /* base class */ + + /* + * Information retrieved from EEPROM. + */ + ar9300_eeprom_t ah_eeprom; + + GAIN_VALUES ah_gain_values; + + u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; + u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; + u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; + u_int16_t ah_assoc_id; + + /* + * Runtime state. + */ + u_int32_t ah_mask_reg; /* copy of AR_IMR */ + u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ + u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ + os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ + struct ar9300_stats ah_stats; /* various statistics */ + RF_HAL_FUNCS ah_rf_hal; + u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ + u_int32_t ah_tx_ok_interrupt_mask; + u_int32_t ah_tx_err_interrupt_mask; + u_int32_t ah_tx_desc_interrupt_mask; + u_int32_t ah_tx_eol_interrupt_mask; + u_int32_t ah_tx_urn_interrupt_mask; + HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; + HAL_SMPS_MODE ah_sm_power_mode; + HAL_BOOL ah_chip_full_sleep; + u_int32_t ah_atim_window; + HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ + u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ + u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ + u_int8_t ah_rx_chainmask_cfg; + u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ + /* Calibration related fields */ + HAL_CAL_TYPES ah_supp_cals; + HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ + HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ + HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ + HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ + HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ +// IQ Cal aliases +#define ah_total_power_meas_i ah_meas0.unsign +#define ah_total_power_meas_q ah_meas1.unsign +#define ah_total_iq_corr_meas ah_meas2.sign + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas0; + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas1; + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas2; + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas3; + u_int16_t ah_cal_samples; + /* end - Calibration related fields */ + u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ + u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ + u_int32_t ah_misc_mode; /* MISC_MODE settings */ + HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ + enum { + AUTO_32KHZ, /* use it if 32kHz crystal present */ + USE_32KHZ, /* do it regardless */ + DONT_USE_32KHZ, /* don't use it regardless */ + } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ + + u_int32_t ah_ofdm_tx_power; + int16_t ah_tx_power_index_offset; + + u_int ah_slot_time; /* user-specified slot time */ + u_int ah_ack_timeout; /* user-specified ack timeout */ + /* + * XXX + * 11g-specific stuff; belongs in the driver. + */ + u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ + u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ + u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ + /* + * RF Silent handling; setup according to the EEPROM. + */ + u_int32_t ah_gpio_select; /* GPIO pin to use */ + u_int32_t ah_polarity; /* polarity to disable RF */ + u_int32_t ah_gpio_bit; /* after init, prev value */ + HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ + +#ifdef ATH_BT_COEX + /* + * Bluetooth coexistence static setup according to the registry + */ + HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ + u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ + u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ + u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ + u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ + u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ + HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ + u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ + /* + * Bluetooth coexistence runtime settings + */ + HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ + u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ + u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ + u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ + u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ + u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ +#endif + + /* + * Generic timer support + */ + u_int32_t ah_avail_gen_timers; /* mask of available timers */ + u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ + u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ + HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ + + /* + * ANI & Radar support. + */ + u_int32_t ah_proc_phy_err; /* Process Phy errs */ + u_int32_t ah_ani_period; /* ani update list period */ + struct ar9300_ani_state *ah_curani; /* cached last reference */ + struct ar9300_ani_state ah_ani[255]; /* per-channel state */ + struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ + struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ + struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ + struct ar9300_ar_state ah_ar; /* AR detector state */ + struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ + struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ + + /* + * Transmit power state. Note these are maintained + * here so they can be retrieved by diagnostic tools. + */ + u_int16_t ah_rates_array[16]; + + /* + * Tx queue interrupt state. + */ + u_int32_t ah_intr_txqs; + + HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ + HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ + + /* + * Extension Channel Rx Clear State + */ + u_int32_t ah_cycle_count; + u_int32_t ah_ctl_busy; + u_int32_t ah_ext_busy; + + /* HT CWM state */ + HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; + u_int8_t ah_tx_chainmask; /* tx chain mask */ + u_int8_t ah_rx_chainmask; /* rx chain mask */ + + u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ + u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ + + int ah_hwp; + void *ah_cal_mem; + HAL_BOOL ah_emu_eeprom; + + HAL_ANI_CMD ah_ani_function; + HAL_BOOL ah_rifs_enabled; + u_int32_t ah_rifs_reg[11]; + u_int32_t ah_rifs_sec_cnt; + + /* open-loop power control */ + u_int32_t original_gain[22]; + int32_t init_pdadc; + int32_t pdadc_delta; + + /* cycle counts for beacon stuck diagnostics */ + u_int32_t ah_cycles; + u_int32_t ah_rx_clear; + u_int32_t ah_rx_frame; + u_int32_t ah_tx_frame; + +#define BB_HANG_SIG1 0 +#define BB_HANG_SIG2 1 +#define BB_HANG_SIG3 2 +#define BB_HANG_SIG4 3 +#define MAC_HANG_SIG1 4 +#define MAC_HANG_SIG2 5 + /* bb hang detection */ + int ah_hang[6]; + hal_hw_hangs_t ah_hang_wars; + /* + * Support for ar9300 multiple INIs + */ + struct ar9300_ini_array ah_ini_pcie_serdes; + struct ar9300_ini_array ah_ini_pcie_serdes_low_power; + struct ar9300_ini_array ah_ini_modes_additional; + struct ar9300_ini_array ah_ini_modes_additional_40mhz; + struct ar9300_ini_array ah_ini_modes_rxgain; + struct ar9300_ini_array ah_ini_modes_rxgain_bounds; + struct ar9300_ini_array ah_ini_modes_txgain; + struct ar9300_ini_array ah_ini_japan2484; + struct ar9300_ini_array ah_ini_radio_post_sys2ant; + struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; + /* + * New INI format starting with Osprey 2.0 INI. + * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) + */ + #define ATH_INI_PRE 0 + #define ATH_INI_CORE 1 + #define ATH_INI_POST 2 + #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) + struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ + struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ + struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ + struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ + + /* + * Added to support DFS postamble array in INI that we need to apply + * in DFS channels + */ + + struct ar9300_ini_array ah_ini_dfs; + +#if ATH_WOW + struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ +#endif + + /* To indicate EEPROM mapping used */ + u_int32_t ah_immunity_vals[6]; + HAL_BOOL ah_immunity_on; + /* + * snap shot of counter register for debug purposes + */ +#ifdef AH_DEBUG + u_int32_t last_tf; + u_int32_t last_rf; + u_int32_t last_rc; + u_int32_t last_cc; +#endif + HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ + u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ + + u_int32_t reg_dmn; /* Regulatory Domain */ + int16_t twice_antenna_gain; /* Antenna Gain */ + u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ + + /* + * Upper limit after factoring in the regulatory max, antenna gain and + * multichain factor. No TxBF, CDD or STBC gain factored + */ + int16_t upper_limit[AR9300_MAX_CHAINS]; + + /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ + int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; + + + /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ + int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; + + /* Transmit Status ring support */ + struct ar9300_txs *ts_ring; + u_int16_t ts_tail; + u_int16_t ts_size; + u_int32_t ts_paddr_start; + u_int32_t ts_paddr_end; + + /* Receive Buffer size */ +#define HAL_RXBUFSIZE_DEFAULT 0xfff + u_int16_t rx_buf_size; + + u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). + + /* Indicate the PLL source clock rate is 25Mhz or not. + * clk_25mhz = 0 by default. + */ + u_int8_t clk_25mhz; + /* For PAPRD uses */ + u_int16_t small_signal_gain[AH_MAX_CHAINS]; + u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; + u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; + u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; + u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ + u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ + u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ + u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ + u_int32_t paprd_training_power; + /* For GreenTx use to store the default tx power */ + u_int8_t ah_default_tx_power[ar9300_rate_size]; + HAL_BOOL ah_paprd_broken; + + /* To store offsets of host interface registers */ + struct { + u_int32_t AR_RC; + u_int32_t AR_WA; + u_int32_t AR_PM_STATE; + u_int32_t AR_H_INFOL; + u_int32_t AR_H_INFOH; + u_int32_t AR_PCIE_PM_CTRL; + u_int32_t AR_HOST_TIMEOUT; + u_int32_t AR_EEPROM; + u_int32_t AR_SREV; + u_int32_t AR_INTR_SYNC_CAUSE; + u_int32_t AR_INTR_SYNC_CAUSE_CLR; + u_int32_t AR_INTR_SYNC_ENABLE; + u_int32_t AR_INTR_ASYNC_MASK; + u_int32_t AR_INTR_SYNC_MASK; + u_int32_t AR_INTR_ASYNC_CAUSE_CLR; + u_int32_t AR_INTR_ASYNC_CAUSE; + u_int32_t AR_INTR_ASYNC_ENABLE; + u_int32_t AR_PCIE_SERDES; + u_int32_t AR_PCIE_SERDES2; + u_int32_t AR_GPIO_OUT; + u_int32_t AR_GPIO_IN; + u_int32_t AR_GPIO_OE_OUT; + u_int32_t AR_GPIO_OE1_OUT; + u_int32_t AR_GPIO_INTR_POL; + u_int32_t AR_GPIO_INPUT_EN_VAL; + u_int32_t AR_GPIO_INPUT_MUX1; + u_int32_t AR_GPIO_INPUT_MUX2; + u_int32_t AR_GPIO_OUTPUT_MUX1; + u_int32_t AR_GPIO_OUTPUT_MUX2; + u_int32_t AR_GPIO_OUTPUT_MUX3; + u_int32_t AR_INPUT_STATE; + u_int32_t AR_SPARE; + u_int32_t AR_PCIE_CORE_RESET_EN; + u_int32_t AR_CLKRUN; + u_int32_t AR_EEPROM_STATUS_DATA; + u_int32_t AR_OBS; + u_int32_t AR_RFSILENT; + u_int32_t AR_GPIO_PDPU; + u_int32_t AR_GPIO_DS; + u_int32_t AR_MISC; + u_int32_t AR_PCIE_MSI; + u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; + u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; + u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; + u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; + u_int32_t AR_TDMA_CCA_CNTL; + u_int32_t AR_TXAPSYNC; + u_int32_t AR_TXSYNC_INIT_SYNC_TMR; + u_int32_t AR_INTR_PRIO_SYNC_CAUSE; + u_int32_t AR_INTR_PRIO_SYNC_ENABLE; + u_int32_t AR_INTR_PRIO_ASYNC_MASK; + u_int32_t AR_INTR_PRIO_SYNC_MASK; + u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; + u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; + } ah_hostifregs; + + u_int32_t ah_enterprise_mode; + u_int32_t ah_radar1; + u_int32_t ah_dc_offset; + HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ + HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ + u_int32_t ah_disable_cck; + HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ + + + /* + * Different types of memory where the calibration data might be stored. + * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. + * To disable searching a type, set its parameter to 0. + */ + int try_dram; + int try_flash; + int try_eeprom; + int try_otp; +#ifdef ATH_CAL_NAND_FLASH + int try_nand; +#endif + /* + * This is where we found the calibration data. + */ + int calibration_data_source; + int calibration_data_source_address; + /* + * This is where we look for the calibration data. must be set before ath_attach() is called + */ + int calibration_data_try; + int calibration_data_try_address; + u_int8_t + tx_iq_cal_enable : 1, + tx_iq_cal_during_agc_cal : 1, + tx_cl_cal_enable : 1; + +#if ATH_SUPPORT_MCI + /* For MCI */ + HAL_BOOL ah_mci_ready; + u_int32_t ah_mci_int_raw; + u_int32_t ah_mci_int_rx_msg; + u_int32_t ah_mci_rx_status; + u_int32_t ah_mci_cont_status; + u_int8_t ah_mci_bt_state; + u_int32_t ah_mci_gpm_addr; + u_int8_t *ah_mci_gpm_buf; + u_int32_t ah_mci_gpm_len; + u_int32_t ah_mci_gpm_idx; + u_int32_t ah_mci_sched_addr; + u_int8_t *ah_mci_sched_buf; + u_int8_t ah_mci_coex_major_version_wlan; + u_int8_t ah_mci_coex_minor_version_wlan; + u_int8_t ah_mci_coex_major_version_bt; + u_int8_t ah_mci_coex_minor_version_bt; + HAL_BOOL ah_mci_coex_bt_version_known; + HAL_BOOL ah_mci_coex_wlan_channels_update; + u_int32_t ah_mci_coex_wlan_channels[4]; + HAL_BOOL ah_mci_coex_2g5g_update; + HAL_BOOL ah_mci_coex_is_2g; + HAL_BOOL ah_mci_query_bt; + HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ + HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ + HAL_BOOL ah_mci_need_flush_btinfo; + HAL_BOOL ah_mci_concur_tx_en; + u_int8_t ah_mci_stomp_low_tx_pri; + u_int8_t ah_mci_stomp_all_tx_pri; + u_int8_t ah_mci_stomp_none_tx_pri; + u_int32_t ah_mci_wlan_cal_seq; + u_int32_t ah_mci_wlan_cal_done; +#if ATH_SUPPORT_AIC + HAL_BOOL ah_aic_enabled; + u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; +#endif +#endif /* ATH_SUPPORT_MCI */ + u_int8_t ah_cac_quiet_enabled; +#if ATH_WOW_OFFLOAD + u_int32_t ah_mcast_filter_l32_set; + u_int32_t ah_mcast_filter_u32_set; +#endif + HAL_BOOL ah_reduced_self_gen_mask; +}; + +#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) + +#define IS_9300_EMU(ah) \ + (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) + +#define ar9300_eep_data_in_flash(_ah) \ + (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) + +#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ + (IS_CHAN_5GHZ(_c) && \ + ((AH_PRIVATE(_ah))->ah_config.ath_hal_fastClockEnable)) + +#if notyet +// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. +&& \ + ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ + (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) +#endif + +/* + * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows + * other cards' DMA reads to complete in the middle of our reset. + */ +#define WAR_6773(x) do { \ + if ((++(x) % 64) == 0) \ + OS_DELAY(1); \ +} while (0) + +#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ + int r; \ + for (r = 0; r < ((iniarray)->ia_rows); r++) { \ + OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ + WAR_6773(regWr); \ + } \ +} while (0) + +#define UPPER_5G_SUB_BANDSTART 5700 +#define MID_5G_SUB_BANDSTART 5400 +#define TRAINPOWER_DB_OFFSET 6 + +#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ + } else { \ + if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ + else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ + { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ + else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) + +#ifdef AH_ASSERT + #define ar9300FeatureNotSupported(feature, ah, func) \ + ath_hal_printf(ah, # feature \ + " not supported but called from %s\n", (func)), \ + hal_assert(0) +#else + #define ar9300FeatureNotSupported(feature, ah, func) \ + ath_hal_printf(ah, # feature \ + " not supported but called from %s\n", (func)) *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***