From owner-p4-projects@FreeBSD.ORG Fri Apr 26 21:49:04 2013 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id CD0C14D9; Fri, 26 Apr 2013 21:49:03 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 8FDEC4D7 for ; Fri, 26 Apr 2013 21:49:03 +0000 (UTC) (envelope-from brooks@freebsd.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:1900:2254:2068::682:0]) by mx1.freebsd.org (Postfix) with ESMTP id 6762B1019 for ; Fri, 26 Apr 2013 21:49:03 +0000 (UTC) Received: from skunkworks.freebsd.org ([127.0.1.74]) by skunkworks.freebsd.org (8.14.6/8.14.6) with ESMTP id r3QLn3N9087667 for ; Fri, 26 Apr 2013 21:49:03 GMT (envelope-from brooks@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.6/8.14.6/Submit) id r3QLn3FA087664 for perforce@freebsd.org; Fri, 26 Apr 2013 21:49:03 GMT (envelope-from brooks@freebsd.org) Date: Fri, 26 Apr 2013 21:49:03 GMT Message-Id: <201304262149.r3QLn3FA087664@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to brooks@freebsd.org using -f From: Brooks Davis Subject: PERFORCE change 228129 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.14 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Apr 2013 21:49:04 -0000 http://p4web.freebsd.org/@@228129?ac=10 Change 228129 by brooks@brooks_zenith on 2013/04/26 21:48:20 Merge 228019 (large TLB support) from cheribsd. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/conf/options.mips#11 integrate .. //depot/projects/ctsrd/beribsd/src/sys/mips/beri/std.beri#5 integrate .. //depot/projects/ctsrd/beribsd/src/sys/mips/include/cpufunc.h#7 integrate .. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cpu.c#4 integrate Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/conf/options.mips#11 (text+ko) ==== @@ -78,6 +78,11 @@ OCTEON_BOARD_CAPK_0100ND opt_cvmx.h # +# Options specific to the BERI and CHERI CPUs. +# +BERI_LARGE_TLB opt_global.h + +# # Options that control the Atheros SoC peripherals # ARGE_DEBUG opt_arge.h ==== //depot/projects/ctsrd/beribsd/src/sys/mips/beri/std.beri#5 (text+ko) ==== @@ -2,3 +2,6 @@ files "../beri/files.beri" cpu CPU_MIPS4KC + +options BERI_LARGE_TLB + ==== //depot/projects/ctsrd/beribsd/src/sys/mips/include/cpufunc.h#7 (text+ko) ==== @@ -242,8 +242,13 @@ #ifdef CPU_CNMIPS MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4); #endif +#ifdef BERI_LARGE_TLB +MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5); +#endif +#if defined(CPU_NLM) || defined(BERI_LARGE_TLB) +MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6); +#endif #ifdef CPU_NLM -MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6); MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7); #endif MIPS_RW32_COP0(count, MIPS_COP_0_COUNT); ==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cpu.c#4 (text+ko) ==== @@ -99,17 +99,29 @@ /* Learn TLB size and L1 cache geometry. */ cfg1 = mips_rd_config1(); -#ifndef CPU_NLM - cpuinfo->tlb_nentries = - ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; -#else + +#if defined(CPU_NLM) /* Account for Extended TLB entries in XLP */ tmp = mips_rd_config6(); cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1; +#elif defined(BERI_LARGE_TLB) + /* Check if we support extended TLB entries and if so activate. */ + tmp = mips_rd_config5(); +#define BERI_CP5_LTLB_SUPPORTED 0x1 + if (tmp & BERI_CP5_LTLB_SUPPORTED) { + /* See how many extra TLB entries we have. */ + tmp = mips_rd_config6(); + cpuinfo->tlb_nentries = (tmp >> 16) + 1; + /* Activate the extended entries. */ + mips_wr_config6(tmp|0x4); + } else +#endif +#if !defined(CPU_NLM) + cpuinfo->tlb_nentries = + ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; #endif - +#if defined(CPU_CNMIPS) /* Add extended TLB size information from config4. */ -#if defined(CPU_CNMIPS) cfg4 = mips_rd_config4(); if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT) cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;