Date: Mon, 10 Mar 1997 16:13:30 -0800 From: David Greenman <dg@root.com> To: Brian McGovern <bmcgover@cisco.com> Cc: Mark Tinguely <tinguely@plains.nodak.edu>, marcio@cyclades.com, hackers@freebsd.org Subject: Re: Question on mapping PCI memory... Message-ID: <199703110013.QAA18267@root.com> In-Reply-To: Your message of "Mon, 10 Mar 1997 16:25:21 EST." <199703102125.QAA16038@bmcgover-pc.cisco.com>
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>0x10 Base Address 1 (Memory address for 9060 controller chip)
>0x14 Base Address 2 (Memory address for 512KB memory window)
>0x18 Base Address 3 (unused)
>0x3C IRQ (0-7)
>
>I then have the lines:
>
>#define CYZ_PCI_BASE_ADDR1 0x10 /* 9060 Controller memory address */
>#define CYZ_PCI_BASE_ADDR2 0x14 /* Memory Window */
>#define CYZ_PCI_IRQ 0x3C /* IRQ */
>
>to make the registers easier to work with. I then have a code chunk that
>does:
>
>vm_offset_t paddr, vaddr;
>
>if (pci_map_mem(config_id, CYZ_PCI_BASE_ADDR2, &vaddr, &paddr) == 0)
> {
> printf("Error mapping shared memory\n");
> return;
> }
>
>
>When run, it complains with: pci_map_mem failed: device's memrange
>0xf880-0xf8ff is incompatible with its bridge's memrange 0x2000000-0xffffffff.
I don't have the time to get sucked into this, but as it turns out, I'm
quite familiar with the PLX 9060. In the code above, you're trying to memory
map the Programmed I/O "ports". Needless to say, you can't do that. :-)
Here is a breakdown of the base address registers for the PLX chip:
/* memory mapped runtime registers */
#define PLX_PCI_BASE_ADDR0 0x10
/* runtime registers via I/O ports */
#define PLX_PCI_BASE_ADDR1 0x14
/* local address space 0 */
#define PLX_PCI_BASE_ADDR2 0x18
/* local address space 1 */
#define PLX_PCI_BASE_ADDR3 0x1c
The Cyclades card is probably using "address space 0" for the 512K of
buffer area.
-DG
David Greenman
Core-team/Principal Architect, The FreeBSD Project
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