Skip site navigation (1)Skip section navigation (2) 
Date:      Mon, 16 Apr 2012 20:20:32 +0000 (UTC)
From:      Pawel Pekala <pawel@FreeBSD.org>
To:        ports-committers@FreeBSD.org, cvs-ports@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   cvs commit: ports/cad/verilog-mode.el Makefile distinfo
Message-ID:  <201204162020.q3GKKWbu092614@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help 
pawel       2012-04-16 20:20:32 UTC

  FreeBSD ports repository

  Modified files:
    cad/verilog-mode.el  Makefile distinfo 
  Log:
  Update to 790
  
  PR:             ports/166209
  Submitted by:   Lowell Gilbert <lowell@be-well.ilk.org>
  
  Revision  Changes    Path
  1.4       +1 -2      ports/cad/verilog-mode.el/Makefile
  1.3       +2 -2      ports/cad/verilog-mode.el/distinfo

Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201204162020.q3GKKWbu092614>