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To: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
cc: current@freebsd.org
Subject: Re: patch for Cyrix/Ti 486SLC/DLC CPU bug 
In-reply-to: Your message of "Wed, 11 Sep 1996 20:39:15 +0900."
             <199609111139.UAA00456@marble.eps.nagoya-u.ac.jp> 
From: David Greenman <dg@root.com>
Reply-To: dg@root.com
Date: Wed, 11 Sep 1996 05:42:29 -0700
Sender: owner-current@freebsd.org
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>Hi, Cyrix/Ti 486 users,
>
>Some version of Cyrix 486SLC/DLC and TI 486DLC have paging related
>bug, and they cause strange segmentation fault and/or page fault
>trap.  I got some information for that bug and fix, and I made the
>patch for FreeBSD-current.
>
>The patch contains:
>
>   1)  FPU exception is handled by interrupt gate (machdep.c).
...
>+ #ifdef CYRIX_486_BUG
>  	setidt(14, &IDTVEC(page),  SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
>+ #else
>+ 	setidt(14, &IDTVEC(page),  SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
>+ #endif

   Your patch changes the page fault exception to an interrupt gate, not the 
FPU exception, but I understand what you meant.

>   2)  The function trap gets fault page address as soon as possible
>       (trap.c).

   I'd be interested to hear more about why this is required. The register
should contain only the information about the last exception - and there
shouldn't be any opportunity to trap again while in trap() before it is read.

>   3)  The functions pmap_update_{1,2}pg don't use LMSW instruction
>       but call pmap_update in cpufunc.h (pmap.c).

   Is this because the Cyrix chip doesn't support selective TLB updates?

-DG

David Greenman
Core-team/Principal Architect, The FreeBSD Project