From owner-p4-projects@FreeBSD.ORG Tue Jun 14 21:03:10 2005 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id C49A416A420; Tue, 14 Jun 2005 21:03:09 +0000 (GMT) X-Original-To: perforce@freebsd.org Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9A13E16A41C for ; Tue, 14 Jun 2005 21:03:09 +0000 (GMT) (envelope-from peter@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 78FE643D4C for ; Tue, 14 Jun 2005 21:03:09 +0000 (GMT) (envelope-from peter@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.1/8.13.1) with ESMTP id j5EL39sJ030831 for ; Tue, 14 Jun 2005 21:03:09 GMT (envelope-from peter@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.1/8.13.1/Submit) id j5EL397a030828 for perforce@freebsd.org; Tue, 14 Jun 2005 21:03:09 GMT (envelope-from peter@freebsd.org) Date: Tue, 14 Jun 2005 21:03:09 GMT Message-Id: <200506142103.j5EL397a030828@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to peter@freebsd.org using -f From: Peter Wemm To: Perforce Change Reviews Cc: Subject: PERFORCE change 78546 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2005 21:03:10 -0000 http://perforce.freebsd.org/chv.cgi?CH=78546 Change 78546 by peter@peter_daintree on 2005/06/14 21:03:07 Properly sync the i386 and amd64 cpu feature flags instead of needless reformatting. While here do the AMD features the same way so that prescott/nocona cores with AMD features will report them. We need to export this info for PG_NX support in i386/PAE. Affected files ... .. //depot/projects/hammer/sys/i386/i386/identcpu.c#22 edit .. //depot/projects/hammer/sys/i386/i386/initcpu.c#12 edit .. //depot/projects/hammer/sys/i386/include/md_var.h#15 edit Differences ... ==== //depot/projects/hammer/sys/i386/i386/identcpu.c#22 (text+ko) ==== @@ -74,9 +74,6 @@ void panicifcpuunsupported(void); static void identifycyrix(void); -#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) -static void print_AMD_features(void); -#endif static void print_AMD_info(void); static void print_AMD_assoc(int i); static void print_transmeta_info(void); @@ -688,42 +685,80 @@ "\040PBE" /* Pending Break Enable */ ); - if (cpu_feature2 != 0) - printf("\n Features2=0x%b", cpu_feature2, - "\020" - "\001SSE3" /* SSE3 */ - "\002" - "\003RSVD2" /* "Reserved" bit 2 */ - "\004MON" /* MONITOR/MWAIT Instructions */ - "\005DS_CPL" /* CPL Qualified Debug Store */ - "\006" /* Machine specific registers */ - "\007" /* Physical address extension */ - "\010EST" /* Enhanced SpeedStep */ - "\011TM2" /* Thermal Monitor 2 */ - "\012" - "\013CNTX-ID" /* L1 context ID available */ - "\014" - "\015" - "\016CX16" /* CMPXCHG16B Instruction */ - "\017" - "\020" - "\021" - "\022" - "\023" - "\024" - "\025" - "\026" - "\027" - "\030" - "\031" - "\032" - "\033" - "\034" - "\035" - "\036" - "\037" - "\040" - ); + if (cpu_feature2 != 0) { + printf("\n Features2=0x%b", cpu_feature2, + "\020" + "\001SSE3" /* SSE3 */ + "\002" + "\003RSVD2" /* "Reserved" bit 2 */ + "\004MON" /* MONITOR/MWAIT Instructions */ + "\005DS_CPL" /* CPL Qualified Debug Store */ + "\006" /* Machine specific registers */ + "\007" /* Physical address extension */ + "\010EST" /* Enhanced SpeedStep */ + "\011TM2" /* Thermal Monitor 2 */ + "\012" + "\013CNTX-ID" /* L1 context ID available */ + "\014" + "\015" + "\016CX16" /* CMPXCHG16B Instruction */ + "\017" + "\020" + "\021" + "\022" + "\023" + "\024" + "\025" + "\026" + "\027" + "\030" + "\031" + "\032" + "\033" + "\034" + "\035" + "\036" + "\037" + "\040" + ); + } + if (amd_feature != 0) { + printf("\n AMD Features=0x%b", amd_feature, + "\020" /* in hex */ + "\001" /* Same */ + "\002" /* Same */ + "\003" /* Same */ + "\004" /* Same */ + "\005" /* Same */ + "\006" /* Same */ + "\007" /* Same */ + "\010" /* Same */ + "\011" /* Same */ + "\012" /* Same */ + "\013" /* Undefined */ + "\014SYSCALL" /* Have SYSCALL/SYSRET */ + "\015" /* Same */ + "\016" /* Same */ + "\017" /* Same */ + "\020" /* Same */ + "\021" /* Same */ + "\022" /* Same */ + "\023" /* Reserved, unknown */ + "\024MP" /* Multiprocessor Capable */ + "\025NX" /* Has EFER.NXE, NX */ + "\026" /* Undefined */ + "\027MMX+" /* AMD MMX Extensions */ + "\030" /* Same */ + "\031" /* Same */ + "\032" /* Undefined */ + "\033" /* Undefined */ + "\034" /* Undefined */ + "\035" /* Undefined */ + "\036LM" /* 64 bit long mode */ + "\0373DNow+" /* AMD 3DNow! Extensions */ + "\0403DNow" /* AMD 3DNow! */ + ); + } /* * If this CPU supports hyperthreading then mention @@ -734,9 +769,6 @@ printf("\n Hyperthreading: %d logical CPUs", (cpu_procinfo & CPUID_HTT_CORES) >> 16); } - if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && - cpu_exthigh >= 0x80000001) - print_AMD_features(); } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { printf(" DIR=0x%04x", cyrix_did); printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); @@ -1101,55 +1133,6 @@ } } -#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) -static void -print_AMD_features(void) -{ - u_int regs[4]; - - /* - * Values taken from AMD Processor Recognition - * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf - */ - do_cpuid(0x80000001, regs); - printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature, - "\020" /* in hex */ - "\001FPU" /* Integral FPU */ - "\002VME" /* Extended VM86 mode support */ - "\003DE" /* Debug extensions */ - "\004PSE" /* 4MByte page tables */ - "\005TSC" /* Timestamp counter */ - "\006MSR" /* Machine specific registers */ - "\007PAE" /* Physical address extension */ - "\010MCE" /* Machine Check support */ - "\011CX8" /* CMPEXCH8 instruction */ - "\012APIC" /* SMP local APIC */ - "\013" - "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */ - "\015MTRR" /* Memory Type Range Registers */ - "\016PGE" /* PG_G (global bit) support */ - "\017MCA" /* Machine Check Architecture */ - "\020ICMOV" /* CMOV instruction */ - "\021PAT" /* Page attributes table */ - "\022PGE36" /* 36 bit address space support */ - "\023RSVD" /* Reserved, unknown */ - "\024MP" /* Multiprocessor Capable */ - "\025NX" /* Has EFER.NXE, NX (no execute pte bit) */ - "\026" - "\027AMIE" /* AMD MMX Instruction Extensions */ - "\030MMX" - "\031FXSAVE" /* FXSAVE/FXRSTOR */ - "\032" - "\033" - "\034" - "\035" - "\036LM" /* Long mode */ - "\037DSP" /* AMD 3DNow! Instruction Extensions */ - "\0403DNow!" /* AMD 3DNow! Instructions */ - ); -} -#endif - static void print_transmeta_info() { ==== //depot/projects/hammer/sys/i386/i386/initcpu.c#12 (text+ko) ==== @@ -80,6 +80,7 @@ int cpu = 0; /* Are we 386, 386sx, 486, etc? */ u_int cpu_feature = 0; /* Feature flags */ u_int cpu_feature2 = 0; /* Feature flags */ +u_int amd_feature = 0; /* Feature flags */ u_int cpu_high = 0; /* Highest arg to CPUID */ u_int cpu_id = 0; /* Stepping ID */ u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */ ==== //depot/projects/hammer/sys/i386/include/md_var.h#15 (text+ko) ==== @@ -45,7 +45,9 @@ extern u_int basemem; /* PA of original top of base memory */ extern int busdma_swi_pending; extern u_int cpu_exthigh; -extern u_int cpu_feature, cpu_feature2; +extern u_int cpu_feature; +extern u_int cpu_feature2; +extern u_int amd_feature; extern u_int cpu_fxsr; extern u_int cpu_high; extern u_int cpu_id;