From owner-svn-src-all@freebsd.org Fri Dec 9 17:16:10 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C7484C6E53E; Fri, 9 Dec 2016 17:16:10 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A1DD6191D; Fri, 9 Dec 2016 17:16:10 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uB9HG9NV071000; Fri, 9 Dec 2016 17:16:09 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uB9HG9fj070998; Fri, 9 Dec 2016 17:16:09 GMT (envelope-from br@FreeBSD.org) Message-Id: <201612091716.uB9HG9fj070998@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Fri, 9 Dec 2016 17:16:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r309739 - head/sys/mips/ingenic X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Dec 2016 17:16:10 -0000 Author: br Date: Fri Dec 9 17:16:09 2016 New Revision: 309739 URL: https://svnweb.freebsd.org/changeset/base/309739 Log: Add registers for jz4780 audio and PDMA controllers. Sponsored by: DARPA, AFRL Added: head/sys/mips/ingenic/jz4780_aic.h (contents, props changed) Modified: head/sys/mips/ingenic/jz4780_pdma.h Added: head/sys/mips/ingenic/jz4780_aic.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/ingenic/jz4780_aic.h Fri Dec 9 17:16:09 2016 (r309739) @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define AICFR 0x00 /* AIC Configuration Register */ +#define AICFR_TFTH_S 16 /* Transmit FIFO threshold for interrupt or DMA request. */ +#define AICFR_TFTH_M (0x1f << AICFR_TFTH_S) +#define AICFR_TFTH(x) ((x) << AICFR_TFTH_S) +#define AICFR_RFTH_S 24 /* Receive FIFO threshold for interrupt or DMA request. */ +#define AICFR_RFTH_M (0x0f << AICFR_RFTH_S) +#define AICFR_RFTH(x) ((x) << AICFR_RFTH_S) +#define AICFR_ICDC (1 << 5) /* Internal CODEC used. */ +#define AICFR_AUSEL (1 << 4) /* Audio Unit Select */ +#define AICFR_RST (1 << 3) /* Reset AIC. */ +#define AICFR_BCKD (1 << 2) /* BIT_CLK Direction. */ +#define AICFR_SYNCD (1 << 1) /* SYNC is generated internally and driven out to the CODEC. */ +#define AICFR_ENB (1 << 0) /* Enable AIC Controller. */ +#define AICCR 0x04 /* AIC Common Control Register */ +#define AICCR_TFLUSH (1 << 8) /* Transmit FIFO Flush. */ +#define AICCR_RFLUSH (1 << 7) /* Receive FIFO Flush. */ +#define AICCR_CHANNEL_S 24 +#define AICCR_CHANNEL_M (0x7 << AICCR_CHANNEL_S) +#define AICCR_CHANNEL_2 (0x1 << AICCR_CHANNEL_S) /* 2 channels, stereo */ +#define AICCR_ISS_S 16 /* Input Sample Size. */ +#define AICCR_ISS_M (0x7 << AICCR_ISS_S) +#define AICCR_ISS_16 (0x1 << AICCR_ISS_S) +#define AICCR_OSS_S 19 /* Output Sample Size. */ +#define AICCR_OSS_M (0x7 << AICCR_OSS_S) +#define AICCR_OSS_16 (0x1 << AICCR_OSS_S) +#define AICCR_RDMS (1 << 15) /* Receive DMA enable. */ +#define AICCR_TDMS (1 << 14) /* Transmit DMA enable. */ +#define AICCR_ENLBF (1 << 2) /* Enable AIC Loop Back Function. */ +#define AICCR_ERPL (1 << 1) /* Enable Playing Back function. */ +#define I2SCR 0x10 /* AIC I2S/MSB-justified Control */ +#define I2SCR_ESCLK (1 << 4) /* Enable SYSCLK output. */ +#define I2SCR_AMSL (1 << 0) /* Select MSB-Justified Operation Mode. */ +#define AICSR 0x14 /* AIC FIFO Status Register Register */ +#define I2SSR 0x1C /* AIC I2S/MSB-justified Status Register */ +#define I2SDIV 0x30 /* AIC I2S/MSB-justified Clock Divider Register */ +#define AICDR 0x34 /* AIC FIFO Data Port Register */ +#define SPENA 0x80 /* SPDIF Enable Register */ +#define SPCTRL 0x84 /* SPDIF Control Register */ +#define SPSTATE 0x88 /* SPDIF Status Register */ +#define SPCFG1 0x8C /* SPDIF Configure 1 Register */ +#define SPCFG2 0x90 /* SPDIF Configure 2 Register */ +#define SPFIFO 0x94 /* SPDIF FIFO Register */ Modified: head/sys/mips/ingenic/jz4780_pdma.h ============================================================================== --- head/sys/mips/ingenic/jz4780_pdma.h Fri Dec 9 16:14:55 2016 (r309738) +++ head/sys/mips/ingenic/jz4780_pdma.h Fri Dec 9 17:16:09 2016 (r309739) @@ -35,13 +35,52 @@ #define PDMA_DTA(n) (0x04 + 0x20 * n) /* Channel n Target Address */ #define PDMA_DTC(n) (0x08 + 0x20 * n) /* Channel n Transfer Count */ #define PDMA_DRT(n) (0x0C + 0x20 * n) /* Channel n Request Source */ +#define DRT_AUTO (1 << 3) /* Auto-request. */ #define PDMA_DCS(n) (0x10 + 0x20 * n) /* Channel n Control/Status */ +#define DCS_DES8 (1 << 30) /* Descriptor 8 Word. */ +#define DCS_AR (1 << 4) /* Address Error. */ +#define DCS_TT (1 << 3) /* Transfer Terminate. */ +#define DCS_HLT (1 << 2) /* DMA halt. */ +#define DCS_CTE (1 << 0) /* Channel transfer enable. */ #define PDMA_DCM(n) (0x14 + 0x20 * n) /* Channel n Command */ +#define DCM_SAI (1 << 23) /* Source Address Increment. */ +#define DCM_DAI (1 << 22) /* Destination Address Increment. */ + +#define DCM_SP_S 14 /* Source port width. */ +#define DCM_SP_M (0x3 << DCM_SP_S) +#define DCM_SP_1 (0x1 << DCM_SP_S) /* 1 byte */ +#define DCM_SP_2 (0x2 << DCM_SP_S) /* 2 bytes */ +#define DCM_SP_4 (0x0 << DCM_SP_S) /* 4 bytes */ + +#define DCM_DP_S 12 /* Destination port width. */ +#define DCM_DP_M (0x3 << DCM_DP_S) +#define DCM_DP_1 (0x1 << DCM_DP_S) /* 1 byte */ +#define DCM_DP_2 (0x2 << DCM_DP_S) /* 2 bytes */ +#define DCM_DP_4 (0x0 << DCM_DP_S) /* 4 bytes */ + +#define DCM_TSZ_S 8 /* Transfer Data Size of a data unit. */ +#define DCM_TSZ_M (0x7 << DCM_TSZ_S) +#define DCM_TSZ_1 (0x1 << DCM_TSZ_S) +#define DCM_TSZ_2 (0x2 << DCM_TSZ_S) +#define DCM_TSZ_4 (0x0 << DCM_TSZ_S) +#define DCM_TSZ_16 (0x3 << DCM_TSZ_S) +#define DCM_TSZ_32 (0x4 << DCM_TSZ_S) +#define DCM_TSZ_64 (0x5 << DCM_TSZ_S) +#define DCM_TSZ_128 (0x6 << DCM_TSZ_S) +#define DCM_TIE (1 << 1) /* Transfer Interrupt Enable (TIE). */ +#define DCM_LINK (1 << 0) /* Descriptor Link Enable. */ #define PDMA_DDA(n) (0x18 + 0x20 * n) /* Channel n Descriptor Address */ #define PDMA_DSD(n) (0x1C + 0x20 * n) /* Channel n Stride Difference */ /* Global Control Registers */ #define PDMA_DMAC 0x1000 /* DMA Control */ +#define DMAC_FMSC (1 << 31) +#define DMAC_INTCC_S 17 +#define DMAC_INTCC_M (0x1f << DMAC_INTCC_S) +#define DMAC_INTCE (1 << 16) /* Permit INTC_IRQ to be bound to one of programmable channel. */ +#define DMAC_HLT (1 << 3) /* Global halt status */ +#define DMAC_AR (1 << 2) /* Global address error status */ +#define DMAC_DMAE (1 << 0) /* Enable DMA. */ #define PDMA_DIRQP 0x1004 /* DMA Interrupt Pending */ #define PDMA_DDB 0x1008 /* DMA Doorbell */ #define PDMA_DDS 0x100C /* DMA Doorbell Set */