From owner-svn-src-all@freebsd.org Sat Nov 25 22:08:41 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 82647DF1A61; Sat, 25 Nov 2017 22:08:41 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4C0B4710DD; Sat, 25 Nov 2017 22:08:41 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vAPM8eaI060323; Sat, 25 Nov 2017 22:08:40 GMT (envelope-from nwhitehorn@FreeBSD.org) Received: (from nwhitehorn@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vAPM8e3o060321; Sat, 25 Nov 2017 22:08:40 GMT (envelope-from nwhitehorn@FreeBSD.org) Message-Id: <201711252208.vAPM8e3o060321@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: nwhitehorn set sender to nwhitehorn@FreeBSD.org using -f From: Nathan Whitehorn Date: Sat, 25 Nov 2017 22:08:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r326210 - head/sys/powerpc/include X-SVN-Group: head X-SVN-Commit-Author: nwhitehorn X-SVN-Commit-Paths: head/sys/powerpc/include X-SVN-Commit-Revision: 326210 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 25 Nov 2017 22:08:41 -0000 Author: nwhitehorn Date: Sat Nov 25 22:08:40 2017 New Revision: 326210 URL: https://svnweb.freebsd.org/changeset/base/326210 Log: Definitions for registers and trap types found on new POWER CPUs. MFC after: 3 weeks Modified: head/sys/powerpc/include/spr.h head/sys/powerpc/include/trap.h Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Sat Nov 25 22:06:40 2017 (r326209) +++ head/sys/powerpc/include/spr.h Sat Nov 25 22:08:40 2017 (r326210) @@ -210,6 +210,11 @@ #define EPCR_DMIUH 0x00400000 #define EPCR_PMGS 0x00200000 #define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */ + +#define SPR_LPCR 0x13e /* Logical Partitioning Control */ +#define LPCR_LPES 0x008 /* Bit 60 */ +#define SPR_LPID 0x13f /* Logical Partitioning Control */ + #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ #define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ Modified: head/sys/powerpc/include/trap.h ============================================================================== --- head/sys/powerpc/include/trap.h Sat Nov 25 22:06:40 2017 (r326209) +++ head/sys/powerpc/include/trap.h Sat Nov 25 22:08:40 2017 (r326210) @@ -77,6 +77,7 @@ #define EXC_DSMISS 0x1200 /* Data store translation miss */ /* Power ISA 2.06+: */ +#define EXC_HEA 0x0e40 /* Hypervisor Emulation Assistance */ #define EXC_VSX 0x0f40 /* VSX Unavailable */ /* The following are available on 4xx and 85xx */