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From: Nathan Whitehorn <nwhitehorn@FreeBSD.org>
Date: Sat, 25 Nov 2017 22:10:11 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r326211 - head/sys/powerpc/aim
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Author: nwhitehorn
Date: Sat Nov 25 22:10:10 2017
New Revision: 326211
URL: https://svnweb.freebsd.org/changeset/base/326211

Log:
  Invalidate TLB at boot using the correct IS settings on newer-than-POWER5
  CPUs.
  
  MFC after:	3 weeks

Modified:
  head/sys/powerpc/aim/moea64_native.c

Modified: head/sys/powerpc/aim/moea64_native.c
==============================================================================
--- head/sys/powerpc/aim/moea64_native.c	Sat Nov 25 22:08:40 2017	(r326210)
+++ head/sys/powerpc/aim/moea64_native.c	Sat Nov 25 22:10:10 2017	(r326211)
@@ -382,7 +382,7 @@ moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
 		__asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
 		    "r"(0));
 
-		for (i = 0; i < 64; i++) {
+		for (i = 0; i < n_slbs; i++) {
 			if (!(slb[i].slbe & SLBE_VALID))
 				continue;
 
@@ -465,9 +465,23 @@ tlbia(void)
 	register_t msr, scratch;
 	#endif
 
+	i = 0xc00; /* IS = 11 */
+	switch (mfpvr() >> 16) {
+	case IBM970:
+	case IBM970FX:
+	case IBM970MP:
+	case IBM970GX:
+	case IBMPOWER4:
+	case IBMPOWER4PLUS:
+	case IBMPOWER5:
+	case IBMPOWER5PLUS:
+		i = 0; /* IS not supported */
+		break;
+	}
+
 	TLBSYNC();
 
-	for (i = 0; i < 0xFF000; i += 0x00001000) {
+	for (; i < 0x200000; i += 0x00001000) {
 		#ifdef __powerpc64__
 		__asm __volatile("tlbiel %0" :: "r"(i));
 		#else