From owner-freebsd-amd64@FreeBSD.ORG Fri Apr 8 17:51:05 2005 Return-Path: Delivered-To: freebsd-amd64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 90F5E16A4CE for ; Fri, 8 Apr 2005 17:51:05 +0000 (GMT) Received: from dragon.NUXI.org (trang.nuxi.com [66.93.134.19]) by mx1.FreeBSD.org (Postfix) with ESMTP id 06CE043D66 for ; Fri, 8 Apr 2005 17:51:04 +0000 (GMT) (envelope-from obrien@NUXI.com) Received: from dragon.NUXI.org (obrien@localhost [127.0.0.1]) by dragon.NUXI.org (8.13.3/8.13.3) with ESMTP id j38Hp3ZQ084373; Fri, 8 Apr 2005 10:51:03 -0700 (PDT) (envelope-from obrien@dragon.NUXI.org) Received: (from obrien@localhost) by dragon.NUXI.org (8.13.3/8.13.1/Submit) id j38Hp3sS084372; Fri, 8 Apr 2005 10:51:03 -0700 (PDT) (envelope-from obrien) Date: Fri, 8 Apr 2005 10:51:03 -0700 From: "David O'Brien" To: "O. Hartmann" Message-ID: <20050408175103.GD81280@dragon.NUXI.org> References: <42540781.7000608@mail.uni-mainz.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <42540781.7000608@mail.uni-mainz.de> X-Operating-System: FreeBSD 6.0-CURRENT Organization: The NUXI BSD Group X-Pgp-Rsa-Fingerprint: B7 4D 3E E9 11 39 5F A3 90 76 5D 69 58 D9 98 7A X-Pgp-Rsa-Keyid: 1024/34F9F9D5 User-Agent: Mutt/1.5.9i cc: freebsd-amd64@freebsd.org Subject: Re: Some questions about Winchester/Newcastle cores of Athlon64 X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list Reply-To: freebsd-amd64@freebsd.org List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Apr 2005 17:51:05 -0000 On Wed, Apr 06, 2005 at 06:00:01PM +0200, O. Hartmann wrote: > In some discussions I read about some memory controler issues of > Winchester based Athlon64 cores. You have to speak specifics not marketing "core" names. I can't even keep them straight -- few within AMD engineering uses them. What silicon revision are you interested in? 'C0', 'CG', 'D', or 'E'? What specific Athlon64 model? Athlon64 939-pin's memory controller is different from 754-pin Athlon64 CPU's. > The CPU will downgrade to DDR333 if 4 double sided memory modules are ^^^ DDR400 > present in a system. This is true for 754-pin (single-channel) rev. C0 & CG CPU's. I think this may be true in some cases for 930-pin. This is simply due to electrical loading issues. AMD documents this in publication 26094: BIOS and Kernel Developers Guild. See 4.1.3 "Maximum DRAM Speed as a Function of Loading". http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF > I also read about a rumor nVidias nForce4 chipset is capable to handle > 4 double sided memory modules with a Winchester based CPU core, If you mean a 939-pin CPU, it doesn't have the problem that the 754-pin CPU's do as it has a dual-channel memory controller. So each channel is only driving 2 DIMM's, not 4 on a channel as a 754-pin CPU would. > but throttling down 1T to 2T access cycles, but remeains in DDR400 > mode. See what the AMD document has to say about it. > Is this also an issue of the Newcastle based CPU cores or is this a bug > in the Winchester cores? Aggg, marketing names again. :-/ > The oncoming Venice/San Diego cores of Athlon64 CPUs are said to be > fixed and capable of driving 4 double sided memory modules. > > Is this weird memory controlling behaviour also an issue on Opteron CPUs? Opteron's will only accept registered(buffered) memory and thus can drive a higher electrical load on the memory bus. -- -- David (obrien@FreeBSD.org)