From nobody Sat May 6 00:59:21 2023 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4QCq2L17Zrz4B1nQ; Sat, 6 May 2023 00:59:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4QCq2L0Sgsz45DN; Sat, 6 May 2023 00:59:22 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1683334762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=7+XMeJ4qTAuovkFK+5aCxpVG89f8H0Q+aWf2pGan+qc=; b=jYm3yCY1LY6lYvGJKj1MEoB4BqIQZEeqhg1fKMTL3mvoCzfGH/tzNUaysIM6xOBTokLGqg ObaM2QuqcrE79AxJVd7lZvIaBf1eqBX0UKARrkYs2C5K/W0uEf/0XHflqCROmjwWdkSiks x5785qra4CV9SlhpWsMNy01m4G3no2V3PTVRgwwpHenuRoa/nF6jzUFwjxC/hzqpUrtdo/ pTly/lfY58QFTmbarHPR/max+h/Q0r3a6JtQuL9W8YK81yHwqWPf23kYpdoItR/gjQh247 zkOnV9a6AX3WDg9TpbWDCN7mOrFDwePGyEKnFyXLRnmJ4U2XeWMD8Pn5hmk5+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1683334762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=7+XMeJ4qTAuovkFK+5aCxpVG89f8H0Q+aWf2pGan+qc=; b=nUrE7Ar9M4K/cybsyZQwvzVjKknTt3ZlBg36k9OR4kxJVdwiC6oBT7BzQbbNOo2L9A9x97 itS3HVlhn7GBjGCdVfwB+HyNuRc4XydU1UTvlvocaMTvDBQviNZsyzqIR/rDmD9sLkBNxb TvDmS9km6IwDaVD1llLL1E4hcqB1klp9esyv2n3lNd26U8WibwgWiGixmKyk4l+14cH1gq jd9kGWGsPadg59I7imjVObbnkiPEtblbwp/33dsW2tv8T0GvWGSUFT7zy2ONbeKldh03+U 52umpz9+SbrPRCGTkdHo1gHAboFd+wRXcf48pB81hg0Qdb6asrGZ0dxfUa0QRw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1683334762; a=rsa-sha256; cv=none; b=aWRHEs4B2AXdf9z4q8v7N+x2szigIAj6susx0JuHxB82Vnyqmy1pnw4j+BH/Bia23ZvS94 8FeF2doPyO1HnkdF6TAuFIY4QUkvO7kvY+cDS2K7Abbboi4+YKVJCuZUlDx4puVeKK6AsK xr2qFhA10ZPjy006ddUWG0urcXCgM8KBZYdnp/vIWsfkoMT0bmpw7MgVvB4nkpuyMTCvUo Sk4quLXwbb73yPN/gLLBTjy8tx2hW+Vh3pw41c8uK8YGymAMlWPACn8RHtdzec/T+eKWYA kxLiBUf/OZtnkZcNF746SoEk0GIdCTvVo8Z/poGZakSiPuu+WVeeGyuuteAUsw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4QCq2K6YbGzGNf; Sat, 6 May 2023 00:59:21 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 3460xLFD052702; Sat, 6 May 2023 00:59:21 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 3460xLLw052701; Sat, 6 May 2023 00:59:21 GMT (envelope-from git) Date: Sat, 6 May 2023 00:59:21 GMT Message-Id: <202305060059.3460xLLw052701@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: "Jason A. Harmening" Subject: git: 651e037e2720 - stable/13 - Intel DMAR: remove parsing of 6-level paging capability List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jah X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 651e037e27207f94c50a3a07d78493c51065da64 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by jah: URL: https://cgit.FreeBSD.org/src/commit/?id=651e037e27207f94c50a3a07d78493c51065da64 commit 651e037e27207f94c50a3a07d78493c51065da64 Author: Jason A. Harmening AuthorDate: 2023-05-01 16:22:39 +0000 Commit: Jason A. Harmening CommitDate: 2023-05-06 00:58:41 +0000 Intel DMAR: remove parsing of 6-level paging capability Early versions of the VT-d spec mentioned 6-level paging support as a possible value for the SAGAW capability, but later versions removed it and SAGAW=0x10 is currently listed as a reserved value. The 6-level (agaw=64) entry in sagaw_bits is furthermore problematic with clang15 because the attempted comparison against 1ULL << 64 in dmar_maxaddr2mgaw() causes the compiler to elide the last iteration of the initial loop, which bypasses the subsequent logic to find the greatest HW-supported address width. This results in 5-level paging always being selected regardless of whether the hardware supports it, which can result address translation failure due to invalid context- entry programming. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D39896 (cherry picked from commit 6f378116e9bf982b8246d033d81cb64d52b24462) --- sys/x86/iommu/intel_utils.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/sys/x86/iommu/intel_utils.c b/sys/x86/iommu/intel_utils.c index 152c7cac3a7d..315ffc8d4160 100644 --- a/sys/x86/iommu/intel_utils.c +++ b/sys/x86/iommu/intel_utils.c @@ -99,9 +99,14 @@ static const struct sagaw_bits_tag { {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL, .pglvl = 4}, {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL, - .pglvl = 5}, - {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL, - .pglvl = 6} + .pglvl = 5} + /* + * 6-level paging (DMAR_CAP_SAGAW_6LVL) is not supported on any + * current VT-d hardware and its SAGAW field value is listed as + * reserved in the VT-d spec. If support is added in the future, + * this structure and the logic in dmar_maxaddr2mgaw() will need + * to change to avoid attempted comparison against 1ULL << 64. + */ }; bool