Date: Fri, 26 Aug 2022 16:35:09 +0000 From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 265974] SMR has several missing barriers Message-ID: <bug-265974-227-NJta9ZgPLw@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-265974-227@https.bugs.freebsd.org/bugzilla/> References: <bug-265974-227@https.bugs.freebsd.org/bugzilla/>
next in thread | previous in thread | raw e-mail | index | archive | help
https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D265974 Mark Johnston <markj@FreeBSD.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|New |Open --- Comment #4 from Mark Johnston <markj@FreeBSD.org> --- I certainly agree with the comment about smr_enter(). On at least arm64, atomic_add_acq_int()'s acquire semantics apply only to the load; subsequent loads can be reordered with the store. I believe this is true with LSE ato= mics as well as the original LL/SC atomics. I also agree that the code is fine = on Intel since atomic instructions prevent store-load reordering. Our atomic(9) documentation doesn't really call out this subtlety. We might have similar bugs elsewhere. I need to think about smr_poll() a bit more. > Moreover, smr_poll() absolutely needs a full memory barrier on entry, the= `atomic_load_acq_int` performed by `smr_poll` aren't sufficient. The suggested patch adds two barriers to smr_poll_scan() and none to smr_poll(), is that intentional? --=20 You are receiving this mail because: You are the assignee for the bug.=
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?bug-265974-227-NJta9ZgPLw>