Date: Wed, 03 Dec 1997 16:24:49 -0800 From: Joe Eykholt <jre@Ipsilon.COM> To: Steve Passe <smp@csn.net> Cc: smp@freebsd.org Subject: Re: SMP Message-ID: <3485F851.3F54BC7E@ipsilon.com> References: <199712032347.QAA10070@Ilsa.StevesCafe.com>
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Steve Passe wrote: > > Hi, > > > 5. The APIC vectors need to be re-arranged into a priority order so > > that interrupts > > don't need to access the I/O APIC to mask off the interrupt during > > handling. > > (Or maybe there's a better way to do this). I noticed that > > level-sensitive > > interrupts are getting taken twice, because the first interrupt only > > masks with CPL, > > so after the EOI and sti, the interrupt is still pending and is taken > > again. Only > > the second time does it get masked in the I/O APIC. Being a central > > sounds like you are describing our "lazy masking" an attempt to skip blocking > an INT unless we get hit a second time. If what you are saying about the > second hit being automatic is true, its something for me to tackle real soon. > Have you actually demonstrated this to occur all times? Or just ocassionally? > OR just via code examination? Could you descibe a specific example that would > help me grok the specific situation? I think so. I added a counter for interrupts deferred due to cpl and that counter was 1/2 the total interrupt count (I counted all interrupts whether deferred or not). All my interrupts were PCI devices (level sensitive), so I'm pretty sure that's what's happening. I also saw a stack trace that showed that the second interrupt occurred just after the first handler did the sti instruction. I've made other changes to the INTR() macro, but I think the same thing would happen in the -current APIC version. Joe
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