Date: Thu, 4 Apr 2002 20:48:04 -0800 (PST) From: Jake Burkholder <jake@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 9088 for review Message-ID: <200204050448.g354m4a56241@freefall.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://people.freebsd.org/~peter/p4db/chv.cgi?CH=9088 Change 9088 by jake@jake_sparc64 on 2002/04/04 20:47:03 Add definitions for register bits. Affected files ... ... //depot/projects/sparc64/sys/dev/se/sereg.h#2 edit Differences ... ==== //depot/projects/sparc64/sys/dev/se/sereg.h#2 (text+ko) ==== @@ -34,11 +34,49 @@ #define SE_RFIFO 0x0 /* receive fifo */ #define SE_XFIFO 0x0 /* transmit fifo */ + #define SE_STAR 0x20 /* status register */ +#define STAR_WFA 0x1 /* wait for acknowledgement */ +#define STAR_CTS 0x2 /* clear to send state */ +#define STAR_CEC 0x4 /* command executing */ +#define STAR_RLI 0x8 /* receive line inactive */ +#define STAR_RRNR 0x10 /* receive receiver not ready */ +#define STAR_XRNR 0x20 /* transmit receiver not ready */ +#define STAR_XFW 0x40 /* transmit fifo write enable */ +#define STAR_XDOV 0x80 /* transmit data overflow */ + #define SE_CMDR 0x20 /* command register */ +#define CMDR_XRES 0x1 /* transmitter reset */ +#define CMDR_XME 0x2 /* transmit message end */ +#define CMDR_XIF 0x4 /* transmit I-frame */ +#define CMDR_XTF 0x8 /* transmit transparent frame */ +#define CMDR_STI 0x10 /* start timer */ +#define CMDR_XREP 0x20 /* transmission repeat */ +#define CMDR_RHR 0x40 /* reset HDLC receiver */ +#define CMDR_RMC 0x80 /* receive message complete */ + #define SE_RSTA 0x21 /* receive status */ +#define RSTA_LA 0x1 /* low byte address compare */ +#define RSTA_CR 0x2 /* command/response */ +#define RSTA_HA0 0x4 /* high byte address compare 0 */ +#define RSTA_HA1 0x8 /* high byte address compare 1 */ +#define RSTA_RAB 0x10 /* receive message aborted */ +#define RSTA_CRC 0x20 /* CRC compare/check */ +#define RSTA_RDO 0x40 /* receive data overflow */ +#define RSTA_VFR 0x80 /* valid frame */ + #define SE_PRE 0x21 /* preamble register */ + #define SE_MODE 0x22 /* mode register */ +#define MODE_TLP 0x1 /* test loop */ +#define MODE_TRS 0x2 /* timer resolution */ +#define MODE_RTS 0x4 /* request to send */ +#define MODE_RAC 0x8 /* receiver active */ +#define MODE_TMD 0x10 /* timer mode */ +#define MODE_ADM 0x20 /* address mode */ +#define MODE_MDS0 0x40 /* mode select 0 */ +#define MODE_MDS1 0x80 /* mode select 1 */ + #define SE_TIMR 0x23 /* timer register */ #define SE_XAD1 0x24 /* transmit address 1 */ #define SE_XAD2 0x25 /* transmit address 2 */ @@ -51,30 +89,129 @@ #define SE_XBCL 0x2a /* transmit byte count low */ #define SE_RBCH 0x2b /* receive byte count high */ #define SE_XBCH 0x2b /* transmit byte count high */ + #define SE_CCR0 0x2c /* channel configuration register 0 */ +#define CCR0_SM0 0x1 /* serial mode 0 */ +#define CCR0_SM1 0x2 /* serial mode 1 */ +#define CCR0_SC0 0x4 /* serial configuration 0 */ +#define CCR0_SC1 0x8 /* serial configuration 1 */ +#define CCR0_SC2 0x10 /* serial configuration 2 */ +#define CCR0_UNUSED0 0x20 /* unused */ +#define CCR0_MSE 0x40 /* master clock enable */ +#define CCR0_PU 0x80 /* power up */ + #define SE_CCR1 0x2d /* channel configuration register 1 */ +#define CCR1_CM0 0x1 /* clock mode 0 */ +#define CCR1_CM1 0x2 /* clock mode 1 */ +#define CCR1_CM2 0x4 /* clock mode 2 */ +#define CCR1_ITF 0x8 /* interframe time fill */ +#define CCR1_ODS 0x10 /* output driver select */ +#define CCR1_GLP 0x20 /* go on loop */ +#define CCR1_GALP 0x40 /* go active on loop */ +#define CCR1_SFLG 0x80 /* enable shared flags */ + #define SE_CCR2 0x2e /* channel configuration register 2 */ +#define CCR2_DIV 0x1 /* data inversion */ +#define CCR2_C32 0x2 /* enable CRC-32 */ +#define CCR2_RWX 0x4 /* read/write exchange */ +#define CCR2_TOE 0x8 /* TxCLK ouput enable */ +#define CCR2_SSEL 0x10 /* clock source select */ +#define CCR2_BDF 0x20 /* baud rate division factor */ +#define CCR2_BR8 0x40 /* baud rate 8 */ +#define CCR2_BR9 0x80 /* baud rate 9 */ +#define CCR2_RCS0 0x10 /* receive clock shift 0 (5) */ +#define CCR2_XCS0 0x20 /* transmit clock shift 0 (5) */ +#define CCR2_SOC0 0x40 /* special output control 0 (0a, 1, 4, 5) */ +#define CCR2_SOC1 0x80 /* special output control 1 (0a, 1, 4, 5) */ + #define SE_CCR3 0x2f /* channel configuration register 3 */ +#define CCR3_PSD 0x1 /* DPLL phase shift disable */ +#define CCR3_XCRC 0x2 /* transmit CRC on/off */ +#define CCR3_RCRC 0x4 /* receive CRC on/off */ +#define CCR3_CRL 0x8 /* CRC reset level */ +#define CCR3_RADD 0x10 /* receive address pushed to rfifo */ +#define CCR3_EPT 0x20 /* enable preamble transmission */ +#define CCR3_PRE0 0x40 /* number of preamble repetition 0 */ +#define CCR3_PRE1 0x80 /* number of preamble repetition 1 */ + #define SE_TSAX 0x30 /* transmit timeslot assignment register */ #define SE_TSAR 0x31 /* receive timeslot assignment register */ #define SE_XCCR 0x32 /* transmit channel capacity register */ -#define SE_RCCR 0x33 /* transmit channel capacity register */ +#define SE_RCCR 0x33 /* receive channel capacity register */ + #define SE_VSTR 0x34 /* version status register */ +#define VSTR_VN0 0x1 /* version number 0 */ +#define VSTR_VN1 0x2 /* version number 1 */ +#define VSTR_VN2 0x4 /* version number 2 */ +#define VSTR_VN3 0x8 /* version number 3 */ +#define VSTR_UNUSED0 0x10 /* unused */ +#define VSTR_UNUSED1 0x20 /* unused */ +#define VSTR_DPLA 0x40 /* DPLL asynchronous */ +#define VSTR_CD 0x80 /* carrier detect */ + #define SE_BGR 0x34 /* baud rate generator register */ #define SE_RLCR 0x35 /* receive frame length check */ #define SE_AML 0x36 /* address mask low */ #define SE_AMH 0x37 /* address mask high */ + #define SE_GIS 0x38 /* global interrupt status */ +#define GIS_ISB0 0x1 /* interrupt status channel B 0 */ +#define GIS_ISB1 0x2 /* interrupt status channel B 1 */ +#define GIS_ISA0 0x4 /* interrupt status channel A 0 */ +#define GIS_ISA1 0x8 /* interrupt status channel A 1 */ +#define GIS_UNUSED0 0x10 /* unused */ +#define GIS_UNUSED1 0x20 /* unused */ +#define GIS_UNUSED2 0x40 /* unused */ +#define GIS_PI 0x80 /* univerisal port interrupt */ + #define SE_IVA 0x38 /* interrupt vector address */ + #define SE_IPC 0x39 /* interrupt port configuration */ +#define IPC_IC0 0x1 /* interrupt configuration 0 */ +#define IPC_IC1 0x2 /* interrupt configuration 1 */ +#define IPC_CASM 0x4 /* cascading mode */ +#define IPC_SLA0 0x8 /* slave address 0 */ +#define IPC_SLA1 0x10 /* slave address 1 */ +#define IPC_UNUSED0 0x20 /* unused */ +#define IPC_UNUSED1 0x40 /* unused */ +#define IPC_VIS 0x80 /* masked interrupts visible */ + #define SE_ISR0 0x3a /* interrupt status 0 */ +#define ISR0_RPF 0x1 /* receive pool full */ +#define ISR0_RFO 0x2 /* receive frame overflow */ +#define ISR0_CDSC 0x4 /* carrier detect status change */ +#define ISR0_PLLA 0x8 /* DPLL asynchronous */ +#define ISR0_PCE 0x10 /* protocol error */ +#define ISR0_RSC 0x20 /* receive status change */ +#define ISR0_RFS 0x40 /* receive frame start */ +#define ISR0_RME 0x80 /* receive frame end */ + #define SE_IMR0 0x3a /* interrupt mask 0 */ + #define SE_ISR1 0x3b /* interrupt status 1 */ +#define ISR1_XPR 0x1 /* transmit pool ready */ +#define ISR1_XMR 0x2 /* transmit message repeat */ +#define ISR1_CSC 0x4 /* clear to send status change */ +#define ISR1_TIN 0x8 /* timer interrupt */ +#define ISR1_XDU 0x10 /* transmit data underrun */ +#define ISR1_AOLP 0x20 /* active on loop */ +#define ISR1_OLP 0x40 /* on loop */ +#define ISR1_EOP 0x80 /* end of poll sequence detected */ + #define SE_IMR1 0x3b /* interrupt mask 1 */ #define SE_PVR 0x3c /* port value register */ #define SE_PIS 0x3d /* port interrupt status */ #define SE_PIM 0x3d /* port interrupt mask */ #define SE_PCR 0x3e /* port configuration register */ + #define SE_CCR4 0x3f /* channel configuration register 4 */ +#define CCR4_RFT0 0x1 /* rfifo threshold level 0 */ +#define CCR4_RFT1 0x2 /* rfifo threshold level 1 */ +#define CCR4_UNUSED0 0x4 /* unused */ +#define CCR4_UNUSED1 0x8 /* unused */ +#define CCR4_ICD 0x10 /* invert polarity of carrier detect signal */ +#define CCR4_TST1 0x20 /* test pin */ +#define CCR4_EBRG 0x40 /* enhanced baud rate generator mode */ +#define CCR4_MCK4 0x80 /* master clock divide by 4 */ #endif To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe p4-projects" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200204050448.g354m4a56241>