From owner-svn-src-head@FreeBSD.ORG Tue Nov 27 00:41:40 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 4C10DE33; Tue, 27 Nov 2012 00:41:40 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 155358FC08; Tue, 27 Nov 2012 00:41:40 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qAR0fdSp022867; Tue, 27 Nov 2012 00:41:39 GMT (envelope-from marcel@svn.freebsd.org) Received: (from marcel@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qAR0fdvE022866; Tue, 27 Nov 2012 00:41:39 GMT (envelope-from marcel@svn.freebsd.org) Message-Id: <201211270041.qAR0fdvE022866@svn.freebsd.org> From: Marcel Moolenaar Date: Tue, 27 Nov 2012 00:41:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r243576 - head/sys/arm/include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Nov 2012 00:41:40 -0000 Author: marcel Date: Tue Nov 27 00:41:39 2012 New Revision: 243576 URL: http://svnweb.freebsd.org/changeset/base/243576 Log: Don't define intr_disable and intr_restore as macros. The macros interfere with structure fields of the same name in drivers, like the intr_disable function pointer in struct cphy_ops in cxgb(4). Instead define intr_disable and intr_restore as inline functions. With intr_disable() an inline function, the I32_bit and F32_bit macros now need to be visible in MI code and given the rather poor names, this is not at all good. Define ARM_CPSR_F32 and ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp) for now. Modified: head/sys/arm/include/cpufunc.h Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Mon Nov 26 23:30:47 2012 (r243575) +++ head/sys/arm/include/cpufunc.h Tue Nov 27 00:41:39 2012 (r243576) @@ -681,20 +681,36 @@ __set_cpsr_c(u_int bic, u_int eor) return ret; } +#define ARM_CPSR_F32 (1 << 6) /* FIQ disable */ +#define ARM_CPSR_I32 (1 << 7) /* IRQ disable */ + #define disable_interrupts(mask) \ - (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ - (mask) & (I32_bit | F32_bit))) + (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \ + (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32))) #define enable_interrupts(mask) \ - (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) + (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0)) #define restore_interrupts(old_cpsr) \ - (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) + (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \ + (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32))) + +static __inline register_t +intr_disable(void) +{ + register_t s; + + s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32); + return (s); +} + +static __inline void +intr_restore(register_t s) +{ + + restore_interrupts(s); +} -#define intr_disable() \ - disable_interrupts(I32_bit | F32_bit) -#define intr_restore(s) \ - restore_interrupts(s) /* Functions to manipulate the CPSR. */ u_int SetCPSR(u_int bic, u_int eor); u_int GetCPSR(void);