Date: Sun, 28 Aug 2022 23:01:33 +0000 From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 265974] SMR has several missing barriers Message-ID: <bug-265974-227-G4NGD3owEA@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-265974-227@https.bugs.freebsd.org/bugzilla/> References: <bug-265974-227@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D265974 --- Comment #10 from Mark Johnston <markj@FreeBSD.org> --- (In reply to Pierre Habouzit from comment #9) dmb st only orders stores, but that's not sufficient to implement a release fence. For what it's worth, LLVM on FreeBSD 14/arm64 compiles atomic_thread_fence(memory_order_release) to a "dmb ish", same as atomic_thread_fence(memory_order_seq_cst). --=20 You are receiving this mail because: You are the assignee for the bug.=
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