From owner-svn-src-all@freebsd.org Mon Mar 25 07:48:53 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8A749155552F; Mon, 25 Mar 2019 07:48:53 +0000 (UTC) (envelope-from allanjude@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 3064484EFC; Mon, 25 Mar 2019 07:48:53 +0000 (UTC) (envelope-from allanjude@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 054024C9B; Mon, 25 Mar 2019 07:48:53 +0000 (UTC) (envelope-from allanjude@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x2P7mqDq020125; Mon, 25 Mar 2019 07:48:52 GMT (envelope-from allanjude@FreeBSD.org) Received: (from allanjude@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x2P7mqKZ020124; Mon, 25 Mar 2019 07:48:52 GMT (envelope-from allanjude@FreeBSD.org) Message-Id: <201903250748.x2P7mqKZ020124@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: allanjude set sender to allanjude@FreeBSD.org using -f From: Allan Jude Date: Mon, 25 Mar 2019 07:48:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r345492 - head/sys/mips/atheros X-SVN-Group: head X-SVN-Commit-Author: allanjude X-SVN-Commit-Paths: head/sys/mips/atheros X-SVN-Commit-Revision: 345492 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 3064484EFC X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.96 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.96)[-0.964,0] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Mar 2019 07:48:53 -0000 Author: allanjude Date: Mon Mar 25 07:48:52 2019 New Revision: 345492 URL: https://svnweb.freebsd.org/changeset/base/345492 Log: The Atheros AR7241 has 20 GPIO pins AR724X_GPIO_PINS used for this family is defined as 18 The datasheet for the AR7241 describes 20 pins, allow all to be used. Submitted by: Hiroki Mori Reviewed by: mizhka Differential Revision: https://reviews.freebsd.org/D17580 Modified: head/sys/mips/atheros/ar71xx_gpio.c head/sys/mips/atheros/ar71xx_gpiovar.h Modified: head/sys/mips/atheros/ar71xx_gpio.c ============================================================================== --- head/sys/mips/atheros/ar71xx_gpio.c Mon Mar 25 07:46:20 2019 (r345491) +++ head/sys/mips/atheros/ar71xx_gpio.c Mon Mar 25 07:48:52 2019 (r345492) @@ -226,9 +226,11 @@ ar71xx_gpio_pin_max(device_t dev, int *maxpin) *maxpin = AR91XX_GPIO_PINS - 1; break; case AR71XX_SOC_AR7240: - case AR71XX_SOC_AR7241: case AR71XX_SOC_AR7242: *maxpin = AR724X_GPIO_PINS - 1; + break; + case AR71XX_SOC_AR7241: + *maxpin = AR7241_GPIO_PINS - 1; break; case AR71XX_SOC_AR9330: case AR71XX_SOC_AR9331: Modified: head/sys/mips/atheros/ar71xx_gpiovar.h ============================================================================== --- head/sys/mips/atheros/ar71xx_gpiovar.h Mon Mar 25 07:46:20 2019 (r345491) +++ head/sys/mips/atheros/ar71xx_gpiovar.h Mon Mar 25 07:48:52 2019 (r345492) @@ -55,6 +55,7 @@ #define AR71XX_GPIO_PINS 12 #define AR724X_GPIO_PINS 18 +#define AR7241_GPIO_PINS 20 #define AR91XX_GPIO_PINS 22 struct ar71xx_gpio_softc {