Date: Thu, 22 Oct 2015 13:18:05 +0000 (UTC) From: David Chisnall <theraven@FreeBSD.org> To: doc-committers@freebsd.org, svn-doc-all@freebsd.org, svn-doc-head@freebsd.org Subject: svn commit: r47638 - head/en_US.ISO8859-1/htdocs/news/status Message-ID: <201510221318.t9MDI5MZ093759@repo.freebsd.org>
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Author: theraven (src,ports committer) Date: Thu Oct 22 13:18:05 2015 New Revision: 47638 URL: https://svnweb.freebsd.org/changeset/doc/47638 Log: Finish an editing pass. A couple of issues remain: - As noted in a comment, one entry refers to a load of nonexistent man pages, with no explanation of what they do. - We are a bit inconsistent about the use of <tt> for command names. - There is some duplication between the ThunderX and ARM64 status reports. Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2015-07-2015-09.xml Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2015-07-2015-09.xml ============================================================================== --- head/en_US.ISO8859-1/htdocs/news/status/report-2015-07-2015-09.xml Thu Oct 22 10:30:45 2015 (r47637) +++ head/en_US.ISO8859-1/htdocs/news/status/report-2015-07-2015-09.xml Thu Oct 22 13:18:05 2015 (r47638) @@ -123,7 +123,7 @@ transparent; applications must be adapted to take advantage of the hardware.</p> - <p>Some I/OAT models support more advanced copying modes, like + <p>Some I/OAT models support more advanced copying modes, such as XOR; these modes are not yet supported in the <tt>ioat(4)</tt> driver.</p> </body> @@ -273,6 +273,9 @@ boot process and keyboard driver as well as the <tt>smbus(4)</tt> driver. It added three new drivers: <tt>ig4(4)</tt>, <tt>cyapa(4)</tt>, and <tt>isl(4)</tt>.</p> + <!-- None of these drivers have man pages (at least, not indexed by the + web man page thing), so how is the reader expected to know what + they do or why they should care? --> <p>Much of the development was originally done in late 2014. Since then, the patches have been massively improved and @@ -888,8 +891,8 @@ ports received a major overhaul to make sure all ports are correctly configured. Dual version support was removed. There is only one mesa version for all supported &os; - versions. The libosmesa port was merged into the Mesa - framework.</p> + versions. The libosmesa port, which provided the off-screen version of + Mesa, was merged into the Mesa framework.</p> <p>Another big item that was included in the Mesa port is OpenCL. There are two GPU-based OpenCL implementations: @@ -1239,7 +1242,7 @@ <help> <task> - <p>The GNOME website is stale. Work is under way to improve + <p>The &os; GNOME website is stale. Work is under way to improve it.</p> </task> @@ -1307,16 +1310,16 @@ specifies the possible effects on memory of out-of-order and speculative execution. More precisely, it specifies the extent to which the machine may visibly reorder memory - accesses in order to optimize performance. Unfortunately, - there are almost as many models as architectures. Moreover, - some architectures, for instance IA32 or Sparcv9 TSO, are + accesses to optimize performance. Unfortunately, + there are almost as many models as architectures. + Some architectures, for example IA32 or Sparcv9 TSO, are relatively strongly ordered. In contrast, others, like PowerPC or ARM, are very relaxed. In effect, atomics define a very relaxed abstract memory model for &os;'s machine-independent code that can be efficiently realized on any of these architectures.</p> - <p>However, most &os; development and testing still happens on + <p>Most &os; development and testing still happens on x86 machines, which, when combined with x86's strongly ordered memory model, leads to errors in the use of atomics, specifically, barriers. In other words, the code is not @@ -1365,7 +1368,7 @@ buffers at the micro-architecural level. So, to ensure sequentially consistent behavior on x86, a store/load barrier needs to be issued, which can be done with an MFENCE - instruction or by any locked RMW operation. The latter + instruction or by any locked read-modify-write operation. The latter approach is recommended by the optimization guides from Intel and AMD. It was noted that careful selection of the scratch memory location, which is modified by the locked RWM @@ -1619,7 +1622,7 @@ </links> <body> - <p>As of the end of Q3 the ports tree holds a bit more than + <p>As of the end of Q3 the ports tree holds just over 25,000 ports, and the PR count is above 2,000. The summer period saw less activity on the ports tree than during the previous quarter, with fewer than 7,000 commits performed by @@ -3115,7 +3118,7 @@ <body> <p>The Allwinner A10 and A20 chips are ARM CPUs found in - increasingly common development boards and other devices, like + increasingly common development boards and other devices, such as the Cubieboard/Cubieboard 2 and the Banana Pi.</p> <p>With the end of a GSoC project by Pratik Singhal, our A10 and
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