From owner-freebsd-arm@FreeBSD.ORG Fri Jan 16 19:14:10 2015 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id AFC065AC for ; Fri, 16 Jan 2015 19:14:10 +0000 (UTC) Received: from d.mail.sonic.net (d.mail.sonic.net [64.142.111.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 9626F1CB for ; Fri, 16 Jan 2015 19:14:10 +0000 (UTC) Received: from zeppelin.tachypleus.net (airbears2-136-152-142-65.AirBears2.Berkeley.EDU [136.152.142.65]) (authenticated bits=0) by d.mail.sonic.net (8.14.9/8.14.9) with ESMTP id t0GJE3OL011150 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Fri, 16 Jan 2015 11:14:03 -0800 Message-ID: <54B962FB.3060705@freebsd.org> Date: Fri, 16 Jan 2015 11:14:03 -0800 From: Nathan Whitehorn User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: freebsd-arm@freebsd.org Subject: Re: interrupt framework References: <54B94D71.90403@linaro.org> In-Reply-To: <54B94D71.90403@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Sonic-CAuth: UmFuZG9tSVZJJH8U6X51YdTlVKkAlZLzy0GWiQ98E3x4TrtyNRnHDa9zE3ZThqlh/AXzrF2+fATwj+/1pCfvvy4+2rgST3KSR1gEdGFwPgw= X-Sonic-ID: C;YC+V1bOd5BGordmh1eMT4g== M;sg/H1bOd5BGordmh1eMT4g== X-Spam-Flag: No X-Sonic-Spam-Details: 0.0/5.0 by cerberusd X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jan 2015 19:14:10 -0000 On 01/16/15 09:42, Julien Grall wrote: > On 15/01/15 13:51, Svatopluk Kraus wrote: >> Hi community, > Hello, > >> I and Michal Meloun have done some work on ARM interrupt framework and >> this is the result. >> >> We've started with intrng project with Ian's WIP changes, have looked >> at Andrew's ARM64 git repository, and this is how we think an >> interrupt framework should look like. We've implemented it with >> removable interrupt controllers in mind (PCI world). It's not finished >> from this point of view, however some functions are more complex >> because of it. > Is there any plan to make this framework generic across all the > architectures? > > Some of our drivers as to create new interrupt controllers to handle > event channel, it's an event notifications provided by Xen which is very > similar to an interrupt (eoi/mask/unmask...). They are used by virtual > devices in order to send/receive interrupts. > > The current code [1] already supports x86 which has a similar > framework [2]. > > If your framework is used on all the architecture (especially ARM, ARM64 > and x86), it would allow us to share the code between the architectures > supported by Xen. > > Regards, > > [1] sys/x86/xen/xen_intr.c > [2] sys/x86/x86/intr_machdep.c > This is very similar to the existing PowerPC code (a little better, based on a first glance) and should be adaptable at least to there. -Nathan