From owner-freebsd-current@FreeBSD.ORG Wed May 6 18:24:26 2015 Return-Path: Delivered-To: current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id F1DCE933; Wed, 6 May 2015 18:24:25 +0000 (UTC) Received: from mail-ig0-x231.google.com (mail-ig0-x231.google.com [IPv6:2607:f8b0:4001:c05::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BA8481AB3; Wed, 6 May 2015 18:24:25 +0000 (UTC) Received: by igbpi8 with SMTP id pi8so103701328igb.0; Wed, 06 May 2015 11:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=vcw8JI0ZFh7d6nd9PRJaIYOdgzAQJlT/59UDmhK6hZg=; b=nMOAuWDKNlDfKezeLfnEzB5yBOp/ISIbcIuOzmQp9hE+WU+WhgP7jfZV+C9299vPDq fe76/cB8XdYKJQjgDfEnvsXjrcuHS/U3xUCt5xXK8Yf0vSR6BOd+vXMoZthoi01f/zAM 4FKoet/bWn+yk8Ca3WMuDkrbKRfQBVYJAWkGplViHiF9v+KPB3f1HJI4DsBwyDEbRGvy 2zVlv5R24UcfUI32/7gzgDjk4gfqLexnDXbsVShmL16/o6BE3NnqZsawT50n+a8dXc07 a2LFPtEAuHB2MY5RmlTByX27xOV6HOg5ZQIXNYlJti2GZZCs1EBge332PrbbLM3e1qYV ZduA== MIME-Version: 1.0 X-Received: by 10.43.71.75 with SMTP id yj11mr3924777icb.69.1430936664433; Wed, 06 May 2015 11:24:24 -0700 (PDT) Received: by 10.107.40.194 with HTTP; Wed, 6 May 2015 11:24:24 -0700 (PDT) In-Reply-To: <11092809.7nmbPfKl0V@ralph.baldwin.cx> References: <11092809.7nmbPfKl0V@ralph.baldwin.cx> Date: Wed, 6 May 2015 14:24:24 -0400 Message-ID: Subject: Re: PCI PF memory decode disable when sizing VF BARs From: Ryan Stone To: John Baldwin Cc: FreeBSD Current , Eric Badger , "current@freebsd.org" Content-Type: text/plain; charset=UTF-8 X-Content-Filtered-By: Mailman/MimeDel 2.1.20 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 May 2015 18:24:26 -0000 On Wed, May 6, 2015 at 11:45 AM, John Baldwin wrote: > There are some devices with BARs in non-standard locations. :( If there is > a flag to just disable the VF bar decoding, then ideally we should just be > doing that and leaving the global decoding flag alone while sizing the VF > BAR. > Disabling SR-IOV BAR decoding in this function is currently redundant, as it's already done in pci_iov.c, but I guess to keep the interface sane it makes sense to do it here too. Something like this then? diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c index b4c6151..c9d7541 100644 --- a/sys/dev/pci/pci.c +++ b/sys/dev/pci/pci.c @@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -62,6 +63,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include @@ -75,6 +77,11 @@ __FBSDID("$FreeBSD$"); (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) +#define PCIR_IS_IOV(cfg, reg) \ + (((cfg)->iov != NULL) && \ + ((reg) >= (cfg)->iov->iov_pos + PCIR_SRIOV_BAR(0)) && \ + ((reg) <= (cfg)->iov->iov_pos + PCIR_SRIOV_BAR(PCIR_MAX_BAR_0))) + static int pci_has_quirk(uint32_t devid, int quirk); static pci_addr_t pci_mapbase(uint64_t mapreg); static const char *pci_maptype(uint64_t mapreg); @@ -2647,7 +2654,8 @@ pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, struct pci_devinfo *dinfo; pci_addr_t map, testval; int ln2range; - uint16_t cmd; + uint32_t restore_reg; + uint16_t cmd, mask; /* * The device ROM BAR is special. It is always a 32-bit @@ -2677,9 +2685,21 @@ pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, * determining the BAR's length since we will be placing it in * a weird state. */ - cmd = pci_read_config(dev, PCIR_COMMAND, 2); - pci_write_config(dev, PCIR_COMMAND, - cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); +#ifdef PCI_IOV + if (PCIR_IS_IOV(&dinfo->cfg, reg)) { + restore_reg = dinfo->cfg.iov->iov_pos + PCIR_SRIOV_CTL; + cmd = pci_read_config(dev, restore_reg, 2); + pci_write_config(dev, restore_reg, cmd & ~PCIM_SRIOV_VF_MSE, 2); + } else +#endif + { + cmd = pci_read_config(dev, PCIR_COMMAND, 2); + mask = PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN; + pci_write_config(dev, PCIR_COMMAND, cmd & ~mask, 2); + restore_reg = PCIR_COMMAND; + } /* * Determine the BAR's length by writing all 1's. The bottom @@ -2701,7 +2721,7 @@ pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, pci_write_config(dev, reg, map, 4); if (ln2range == 64) pci_write_config(dev, reg + 4, map >> 32, 4); - pci_write_config(dev, PCIR_COMMAND, cmd, 2); + pci_write_config(dev, restore_reg, cmd, 2); *mapp = map; *testvalp = testval;