Date: Fri, 17 Jul 2020 22:04:33 -0700 From: Mark Millard <marklmi@yahoo.com> To: "mmel@freebsd.org" <mmel@FreeBSD.org>, freebsd-arm <freebsd-arm@freebsd.org> Subject: Re: Rock64 head -r363021 -> -r363123 kernel upgrade: hangs after "rk_tsadc0: <RockChip temperature sensors> mem ... irq 22 on ofwbus0" Message-ID: <A5223224-A176-4D34-AA8E-B6245A54E8EC@yahoo.com> In-Reply-To: <78EA1B36-904C-4CB5-89D1-D6873F4EB981@yahoo.com> References: <7BB9973C-CCC4-4599-98D5-864BEBECE3DF@yahoo.com> <DCA57F06-4735-4A68-8201-C48A25B937C6@yahoo.com> <78EA1B36-904C-4CB5-89D1-D6873F4EB981@yahoo.com>
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On 2020-Jul-13, at 19:42, Mark Millard <marklmi at yahoo.com> wrote: > On 2020-Jul-13, at 02:10, Mark Millard <marklmi at yahoo.com> wrote: >=20 >> On 2020-Jul-13, at 00:59, Mark Millard <marklmi at yahoo.com> wrote: >>=20 >>> With boot -v the kernel crashes instead of being >>> silently-hung: >>>=20 >>> . . . >>> generic_timer0: <ARMv8 Generic Timer> irq 4,5,6,7 on ofwbus0 >>> Timecounter "ARM MPCore Timecounter" frequency 24000000 Hz quality = 1000 >>> Event timer "ARM MPCore Eventtimer" frequency 24000000 Hz quality = 1000 >>> rk_tsadc0: <RockChip temperature sensors> mem 0xff250000-0xff2500ff = irq 22 on ofwbus0 >>> panic: stack overflow detected; backtrace may be corrupted >>> cpuid =3D 0 >>> time =3D 1 >>> KDB: stack backtrace: >> . . . >>=20 >> Trying artifact.ci.freebsd.org debug kernels >> for an approximate bisect: >>=20 >> -r363121 works. >> -r363122 has no aarch64 artifacts. >> -r363123 fails. >>=20 >> (So the specifics of my personal builds are >> not involved.) >>=20 >>=20 >> -r363122 is: >>=20 >> Author: mmel >> Date: Sun Jul 12 07:42:21 2020 >> New Revision: 363122 >> URL:=20 >> https://svnweb.freebsd.org/changeset/base/363122 >>=20 >> Log: >> Assigned clocks: fix off-by-one bug, don't leak allocated memory. >>=20 >> MFC after: 1 week >> . . . >>=20 >>=20 >> -r363123 is: >>=20 >> Author: mmel >> Date: Sun Jul 12 07:59:15 2020 >> New Revision: 363123 >> URL:=20 >> https://svnweb.freebsd.org/changeset/base/363123 >>=20 >> Log: >> Reverse the processing order of assigned clocks property. >> Linux processes these clocks in reverse order and some DT relies >> on this fact. For example, the frequency setting for a given PLL >> is the last in the list, preceded by the frequency setting of its >> following divider or so... >>=20 >> MFC after: 1 week >>=20 >> . . . >>=20 >=20 > Updating from: >=20 > U-Boot TPL 2020.04 (Apr 25 2020 - 07:18:42) > U-Boot SPL 2020.04 (Apr 25 2020 - 07:18:42 +0000) > U-Boot 2020.04 (Apr 25 2020 - 07:19:22 +0000) >=20 > to sysutils/u-boot-rock64 and sysutils/u-boot-master > producing : >=20 > U-Boot TPL 2020.07 (Jul 13 2020 - 18:51:17) > U-Boot SPL 2020.07 (Jul 13 2020 - 18:51:17 +0000) > U-Boot 2020.07 (Jul 13 2020 - 18:56:13 +0000) >=20 > made no difference when installed and tested. >=20 > (The detailed last-messasge point does seem to > vary generally, so I've not considered that when > comparing. It still hangs up with the updated > sysutils/u-boot-rock64 related materials.) >=20 As head -r363123 was a change in the order of processing assigned clocks I show below what u-boot "fdt print /" reports, also how I found the address for setting up to print. May be someone will recognize if the Rock64 dtb ordering and the new order of processing are incompatible in some specific place(s). (I've not done well at figuring out how to get evidence of the actual problem.) There are: A) 4 assigned-clocks=3D lines B) 3 assigned-clock-parents=3D lines C) 2 assigned-clock-rates=3D lines tsadc@ff250000, clock-controller@ff440000, syscon@ff450000's usb2-phy@100, and ethernet@ff540000 have such lines. clock-controller@ff440000 uses notations: assigned-clocks =3D * 0x00000000080f4094 [0x000000f8]; and: assigned-clock-rates =3D * 0x00000000080f41c8 = [0x0000007c]; which are not like used in the others. Booting attempts report: Using DTB provided by EFI at 0x80f0000. So in u-boot . . . (I show the whole thing since I do not know how various things might be related.) =3D> fdt addr 0x80f0000 =3D> fdt print / / { serial-number =3D "987bc4c7d9280466"; compatible =3D "pine64,rock64", "rockchip,rk3328"; interrupt-parent =3D <0x00000059>; #address-cells =3D <0x00000002>; #size-cells =3D <0x00000002>; model =3D "Pine64 Rock64"; memory { reg =3D <0x00000000 0x00200000 0x00000000 0xfee00000>; device_type =3D "memory"; }; aliases { serial0 =3D "/serial@ff110000"; serial1 =3D "/serial@ff120000"; serial2 =3D "/serial@ff130000"; i2c0 =3D "/i2c@ff150000"; i2c1 =3D "/i2c@ff160000"; i2c2 =3D "/i2c@ff170000"; i2c3 =3D "/i2c@ff180000"; ethernet0 =3D "/ethernet@ff540000"; ethernet1 =3D "/ethernet@ff550000"; }; cpus { #address-cells =3D <0x00000002>; #size-cells =3D <0x00000000>; cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x00000000 0x00000000>; clocks =3D <0x0000004b 0x00000006>; #cooling-cells =3D <0x00000002>; cpu-idle-states =3D <0x00000005>; dynamic-power-coefficient =3D <0x00000078>; enable-method =3D "psci"; next-level-cache =3D <0x00000006>; operating-points-v2 =3D <0x00000007>; cpu-supply =3D <0x00000022>; phandle =3D <0x00000001>; }; cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x00000000 0x00000001>; clocks =3D <0x0000004b 0x00000006>; #cooling-cells =3D <0x00000002>; cpu-idle-states =3D <0x00000005>; dynamic-power-coefficient =3D <0x00000078>; enable-method =3D "psci"; next-level-cache =3D <0x00000006>; operating-points-v2 =3D <0x00000007>; cpu-supply =3D <0x00000022>; phandle =3D <0x00000002>; }; cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x00000000 0x00000002>; clocks =3D <0x0000004b 0x00000006>; #cooling-cells =3D <0x00000002>; cpu-idle-states =3D <0x00000005>; dynamic-power-coefficient =3D <0x00000078>; enable-method =3D "psci"; next-level-cache =3D <0x00000006>; operating-points-v2 =3D <0x00000007>; cpu-supply =3D <0x00000022>; phandle =3D <0x00000003>; }; cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x00000000 0x00000003>; clocks =3D <0x0000004b 0x00000006>; #cooling-cells =3D <0x00000002>; cpu-idle-states =3D <0x00000005>; dynamic-power-coefficient =3D <0x00000078>; enable-method =3D "psci"; next-level-cache =3D <0x00000006>; operating-points-v2 =3D <0x00000007>; cpu-supply =3D <0x00000022>; phandle =3D <0x00000004>; }; idle-states { entry-method =3D "psci"; cpu-sleep { compatible =3D "arm,idle-state"; local-timer-stop; arm,psci-suspend-param =3D <0x00010000>; entry-latency-us =3D <0x00000078>; exit-latency-us =3D <0x000000fa>; min-residency-us =3D <0x00000384>; phandle =3D <0x00000005>; }; }; l2-cache0 { compatible =3D "cache"; phandle =3D <0x00000006>; }; }; opp_table0 { compatible =3D "operating-points-v2"; opp-shared; phandle =3D <0x00000007>; opp-408000000 { opp-hz =3D <0x00000000 0x18519600>; opp-microvolt =3D <0x000e7ef0>; clock-latency-ns =3D <0x00009c40>; opp-suspend; }; opp-600000000 { opp-hz =3D <0x00000000 0x23c34600>; opp-microvolt =3D <0x000e7ef0>; clock-latency-ns =3D <0x00009c40>; }; opp-816000000 { opp-hz =3D <0x00000000 0x30a32c00>; opp-microvolt =3D <0x000f4240>; clock-latency-ns =3D <0x00009c40>; }; opp-1008000000 { opp-hz =3D <0x00000000 0x3c14dc00>; opp-microvolt =3D <0x0010c8e0>; clock-latency-ns =3D <0x00009c40>; }; opp-1200000000 { opp-hz =3D <0x00000000 0x47868c00>; opp-microvolt =3D <0x0012b128>; clock-latency-ns =3D <0x00009c40>; }; opp-1296000000 { opp-hz =3D <0x00000000 0x4d3f6400>; opp-microvolt =3D <0x0013d620>; clock-latency-ns =3D <0x00009c40>; }; }; bus { compatible =3D "simple-bus"; #address-cells =3D <0x00000002>; #size-cells =3D <0x00000002>; ranges; phandle =3D <0x00000008>; dmac@ff1f0000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x00000000 0xff1f0000 0x00000000 = 0x00004000>; interrupts =3D <0x00000000 0x00000000 0x00000004 = 0x00000000 0x00000001 0x00000004>; clocks =3D <0x0000004b 0x00000086>; clock-names =3D "apb_pclk"; #dma-cells =3D <0x00000001>; phandle =3D <0x00000009>; }; }; analog-sound { compatible =3D "simple-audio-card"; simple-audio-card,format =3D "i2s"; simple-audio-card,mclk-fs =3D <0x00000100>; simple-audio-card,name =3D "Analog"; status =3D "disabled"; phandle =3D <0x0000000a>; simple-audio-card,cpu { sound-dai =3D <0x0000000f>; }; simple-audio-card,codec { sound-dai =3D <0x00000048>; }; }; arm-pmu { compatible =3D "arm,cortex-a53-pmu"; interrupts =3D <0x00000000 0x00000064 0x00000004 = 0x00000000 0x00000065 0x00000004 0x00000000 0x00000066 0x00000004 = 0x00000000 0x00000067 0x00000004>; interrupt-affinity =3D <0x00000001 0x00000002 0x00000003 = 0x00000004>; }; display-subsystem { compatible =3D "rockchip,display-subsystem"; ports =3D <0x00000042>; phandle =3D <0x0000000b>; }; hdmi-sound { compatible =3D "simple-audio-card"; simple-audio-card,format =3D "i2s"; simple-audio-card,mclk-fs =3D <0x00000080>; simple-audio-card,name =3D "HDMI"; status =3D "disabled"; phandle =3D <0x0000000c>; simple-audio-card,cpu { sound-dai =3D <0x0000000e>; }; simple-audio-card,codec { sound-dai =3D <0x00000045>; }; }; psci { compatible =3D "arm,psci-1.0", "arm,psci-0.2"; method =3D "smc"; }; timer { compatible =3D "arm,armv8-timer"; interrupts =3D <0x00000001 0x0000000d 0x00000f08 = 0x00000001 0x0000000e 0x00000f08 0x00000001 0x0000000b 0x00000f08 = 0x00000001 0x0000000a 0x00000f08>; }; xin24m { compatible =3D "fixed-clock"; #clock-cells =3D <0x00000000>; clock-frequency =3D <0x016e3600>; clock-output-names =3D "xin24m"; phandle =3D <0x0000000d>; }; i2s@ff000000 { compatible =3D "rockchip,rk3328-i2s", = "rockchip,rk3066-i2s"; reg =3D <0x00000000 0xff000000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x0000001a 0x00000004>; clocks =3D <0x0000004b 0x00000029 0x0000004b = 0x00000137>; clock-names =3D "i2s_clk", "i2s_hclk"; dmas =3D <0x00000009 0x0000000b 0x00000009 0x0000000c>; dma-names =3D "tx", "rx"; #sound-dai-cells =3D <0x00000000>; status =3D "disabled"; phandle =3D <0x0000000e>; }; i2s@ff010000 { compatible =3D "rockchip,rk3328-i2s", = "rockchip,rk3066-i2s"; reg =3D <0x00000000 0xff010000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x0000001b 0x00000004>; clocks =3D <0x0000004b 0x0000002a 0x0000004b = 0x00000138>; clock-names =3D "i2s_clk", "i2s_hclk"; dmas =3D <0x00000009 0x0000000e 0x00000009 0x0000000f>; dma-names =3D "tx", "rx"; #sound-dai-cells =3D <0x00000000>; status =3D "okay"; phandle =3D <0x0000000f>; port { phandle =3D <0x00000010>; endpoint { dai-format =3D "i2s"; mclk-fs =3D <0x00000100>; remote-endpoint =3D <0x00000049>; phandle =3D <0x00000011>; }; }; }; i2s@ff020000 { compatible =3D "rockchip,rk3328-i2s", = "rockchip,rk3066-i2s"; reg =3D <0x00000000 0xff020000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x0000001c 0x00000004>; clocks =3D <0x0000004b 0x0000002b 0x0000004b = 0x00000139>; clock-names =3D "i2s_clk", "i2s_hclk"; dmas =3D <0x00000009 0x00000000 0x00000009 0x00000001>; dma-names =3D "tx", "rx"; #sound-dai-cells =3D <0x00000000>; status =3D "disabled"; phandle =3D <0x00000012>; }; spdif@ff030000 { compatible =3D "rockchip,rk3328-spdif"; reg =3D <0x00000000 0xff030000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x0000001d 0x00000004>; clocks =3D <0x0000004b 0x0000002e 0x0000004b = 0x0000013a>; clock-names =3D "mclk", "hclk"; dmas =3D <0x00000009 0x0000000a>; dma-names =3D "tx"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000b3>; #sound-dai-cells =3D <0x00000000>; status =3D "okay"; phandle =3D <0x00000013>; port { phandle =3D <0x00000014>; endpoint { remote-endpoint =3D <0x000000f0>; phandle =3D <0x00000015>; }; }; }; pdm@ff040000 { compatible =3D "rockchip,pdm"; reg =3D <0x00000000 0xff040000 0x00000000 0x00001000>; clocks =3D <0x0000004b 0x0000003d 0x0000004b = 0x00000152>; clock-names =3D "pdm_clk", "pdm_hclk"; dmas =3D <0x00000009 0x00000010>; dma-names =3D "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <0x00000075 0x00000077 0x00000078 = 0x00000079 0x0000007a>; pinctrl-1 =3D <0x0000007b 0x0000007c 0x0000007d = 0x0000007e 0x0000007f>; status =3D "disabled"; phandle =3D <0x00000016>; }; syscon@ff100000 { compatible =3D "rockchip,rk3328-grf", "syscon", = "simple-mfd"; reg =3D <0x00000000 0xff100000 0x00000000 0x00001000>; phandle =3D <0x00000017>; io-domains { compatible =3D = "rockchip,rk3328-io-voltage-domain"; status =3D "okay"; vccio1-supply =3D <0x00000024>; vccio2-supply =3D <0x00000026>; vccio3-supply =3D <0x00000024>; vccio4-supply =3D <0x00000025>; vccio5-supply =3D <0x00000024>; vccio6-supply =3D <0x00000024>; pmuio-supply =3D <0x00000024>; phandle =3D <0x00000018>; }; grf-gpio { compatible =3D "rockchip,rk3328-grf-gpio"; gpio-controller; #gpio-cells =3D <0x00000002>; phandle =3D <0x00000019>; }; power-controller { compatible =3D = "rockchip,rk3328-power-controller"; #power-domain-cells =3D <0x00000001>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; phandle =3D <0x0000001a>; pd_hevc@6 { reg =3D <0x00000006>; }; pd_video@5 { reg =3D <0x00000005>; }; pd_vpu@8 { reg =3D <0x00000008>; clocks =3D <0x0000004b 0x0000008f = 0x0000004b 0x00000146>; }; }; reboot-mode { compatible =3D "syscon-reboot-mode"; offset =3D <0x000005c8>; mode-normal =3D "RB=E2=88=9A"; mode-recovery =3D <0x5242c303>; mode-bootloader =3D <0x5242c309>; mode-loader =3D <0x5242c301>; }; }; serial@ff110000 { compatible =3D "rockchip,rk3328-uart", = "snps,dw-apb-uart"; reg =3D <0x00000000 0xff110000 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000037 0x00000004>; clocks =3D <0x0000004b 0x00000026 0x0000004b = 0x000000d2>; clock-names =3D "baudclk", "apb_pclk"; dmas =3D <0x00000009 0x00000002 0x00000009 0x00000003>; dma-names =3D "tx", "rx"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x00000083 0x00000084 0x00000085>; reg-io-width =3D <0x00000004>; reg-shift =3D <0x00000002>; status =3D "disabled"; phandle =3D <0x0000001b>; }; serial@ff120000 { compatible =3D "rockchip,rk3328-uart", = "snps,dw-apb-uart"; reg =3D <0x00000000 0xff120000 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000038 0x00000004>; clocks =3D <0x0000004b 0x00000027 0x0000004b = 0x000000d3>; clock-names =3D "baudclk", "apb_pclk"; dmas =3D <0x00000009 0x00000004 0x00000009 0x00000005>; dma-names =3D "tx", "rx"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x00000087 0x00000088 0x00000089>; reg-io-width =3D <0x00000004>; reg-shift =3D <0x00000002>; status =3D "disabled"; phandle =3D <0x0000001c>; }; serial@ff130000 { compatible =3D "rockchip,rk3328-uart", = "snps,dw-apb-uart"; reg =3D <0x00000000 0xff130000 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000039 0x00000004>; clocks =3D <0x0000004b 0x00000028 0x0000004b = 0x000000d4>; clock-names =3D "baudclk", "apb_pclk"; dmas =3D <0x00000009 0x00000006 0x00000009 0x00000007>; dma-names =3D "tx", "rx"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x0000008c>; reg-io-width =3D <0x00000004>; reg-shift =3D <0x00000002>; status =3D "okay"; phandle =3D <0x0000001d>; }; i2c@ff150000 { compatible =3D "rockchip,rk3328-i2c", = "rockchip,rk3399-i2c"; reg =3D <0x00000000 0xff150000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x00000024 0x00000004>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; clocks =3D <0x0000004b 0x00000037 0x0000004b = 0x000000cd>; clock-names =3D "i2c", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x0000006f>; status =3D "disabled"; phandle =3D <0x0000001e>; }; i2c@ff160000 { compatible =3D "rockchip,rk3328-i2c", = "rockchip,rk3399-i2c"; reg =3D <0x00000000 0xff160000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x00000025 0x00000004>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; clocks =3D <0x0000004b 0x00000038 0x0000004b = 0x000000ce>; clock-names =3D "i2c", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x00000070>; status =3D "okay"; phandle =3D <0x0000001f>; pmic@18 { compatible =3D "rockchip,rk805"; reg =3D <0x00000018>; interrupt-parent =3D <0x0000005d>; interrupts =3D <0x00000006 0x00000008>; #clock-cells =3D <0x00000001>; clock-output-names =3D "xin32k", = "rk805-clkout2"; gpio-controller; #gpio-cells =3D <0x00000002>; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000e9>; rockchip,system-power-controller; wakeup-source; vcc1-supply =3D <0x000000ef>; vcc2-supply =3D <0x000000ef>; vcc3-supply =3D <0x000000ef>; vcc4-supply =3D <0x000000ef>; vcc5-supply =3D <0x00000024>; vcc6-supply =3D <0x000000ef>; phandle =3D <0x00000020>; regulators { DCDC_REG1 { regulator-name =3D "vdd_logic"; regulator-min-microvolt =3D = <0x000adf34>; regulator-max-microvolt =3D = <0x00162010>; regulator-ramp-delay =3D = <0x000030d4>; regulator-always-on; regulator-boot-on; phandle =3D <0x00000021>; regulator-state-mem { regulator-on-in-suspend; = regulator-suspend-microvolt =3D <0x000f4240>; }; }; DCDC_REG2 { regulator-name =3D "vdd_arm"; regulator-min-microvolt =3D = <0x000adf34>; regulator-max-microvolt =3D = <0x00162010>; regulator-ramp-delay =3D = <0x000030d4>; regulator-always-on; regulator-boot-on; phandle =3D <0x00000022>; regulator-state-mem { regulator-on-in-suspend; = regulator-suspend-microvolt =3D <0x000e7ef0>; }; }; DCDC_REG3 { regulator-name =3D "vcc_ddr"; regulator-always-on; regulator-boot-on; phandle =3D <0x00000023>; regulator-state-mem { regulator-on-in-suspend; }; }; DCDC_REG4 { regulator-name =3D "vcc_io"; regulator-min-microvolt =3D = <0x00325aa0>; regulator-max-microvolt =3D = <0x00325aa0>; regulator-always-on; regulator-boot-on; phandle =3D <0x00000024>; regulator-state-mem { regulator-on-in-suspend; = regulator-suspend-microvolt =3D <0x00325aa0>; }; }; LDO_REG1 { regulator-name =3D "vcc_18"; regulator-min-microvolt =3D = <0x001b7740>; regulator-max-microvolt =3D = <0x001b7740>; regulator-always-on; regulator-boot-on; phandle =3D <0x00000025>; regulator-state-mem { regulator-on-in-suspend; = regulator-suspend-microvolt =3D <0x001b7740>; }; }; LDO_REG2 { regulator-name =3D "vcc18_emmc"; regulator-min-microvolt =3D = <0x001b7740>; regulator-max-microvolt =3D = <0x001b7740>; regulator-always-on; regulator-boot-on; phandle =3D <0x00000026>; regulator-state-mem { regulator-on-in-suspend; = regulator-suspend-microvolt =3D <0x001b7740>; }; }; LDO_REG3 { regulator-name =3D "vdd_10"; regulator-min-microvolt =3D = <0x000f4240>; regulator-max-microvolt =3D = <0x000f4240>; regulator-always-on; regulator-boot-on; phandle =3D <0x00000027>; regulator-state-mem { regulator-on-in-suspend; = regulator-suspend-microvolt =3D <0x000f4240>; }; }; }; }; }; i2c@ff170000 { compatible =3D "rockchip,rk3328-i2c", = "rockchip,rk3399-i2c"; reg =3D <0x00000000 0xff170000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x00000026 0x00000004>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; clocks =3D <0x0000004b 0x00000039 0x0000004b = 0x000000cf>; clock-names =3D "i2c", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x00000071>; status =3D "disabled"; phandle =3D <0x00000028>; }; i2c@ff180000 { compatible =3D "rockchip,rk3328-i2c", = "rockchip,rk3399-i2c"; reg =3D <0x00000000 0xff180000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x00000027 0x00000004>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; clocks =3D <0x0000004b 0x0000003a 0x0000004b = 0x000000d0>; clock-names =3D "i2c", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x00000072>; status =3D "disabled"; phandle =3D <0x00000029>; }; spi@ff190000 { compatible =3D "rockchip,rk3328-spi", = "rockchip,rk3066-spi"; reg =3D <0x00000000 0xff190000 0x00000000 0x00001000>; interrupts =3D <0x00000000 0x00000031 0x00000004>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; clocks =3D <0x0000004b 0x00000020 0x0000004b = 0x000000d1>; clock-names =3D "spiclk", "apb_pclk"; dmas =3D <0x00000009 0x00000008 0x00000009 0x00000009>; dma-names =3D "tx", "rx"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x00000097 0x00000099 0x0000009a = 0x00000098>; status =3D "okay"; phandle =3D <0x0000002a>; spiflash@0 { compatible =3D "jedec,spi-nor"; reg =3D <0x00000000>; spi-max-frequency =3D <0x02faf080>; }; }; watchdog@ff1a0000 { compatible =3D "snps,dw-wdt"; reg =3D <0x00000000 0xff1a0000 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000028 0x00000004>; clocks =3D <0x0000004b 0x000000ec>; phandle =3D <0x0000002b>; }; pwm@ff1b0000 { compatible =3D "rockchip,rk3328-pwm"; reg =3D <0x00000000 0xff1b0000 0x00000000 0x00000010>; clocks =3D <0x0000004b 0x0000003c 0x0000004b = 0x000000d6>; clock-names =3D "pwm", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000d7>; #pwm-cells =3D <0x00000003>; status =3D "disabled"; phandle =3D <0x0000002c>; }; pwm@ff1b0010 { compatible =3D "rockchip,rk3328-pwm"; reg =3D <0x00000000 0xff1b0010 0x00000000 0x00000010>; clocks =3D <0x0000004b 0x0000003c 0x0000004b = 0x000000d6>; clock-names =3D "pwm", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000d8>; #pwm-cells =3D <0x00000003>; status =3D "disabled"; phandle =3D <0x0000002d>; }; pwm@ff1b0020 { compatible =3D "rockchip,rk3328-pwm"; reg =3D <0x00000000 0xff1b0020 0x00000000 0x00000010>; clocks =3D <0x0000004b 0x0000003c 0x0000004b = 0x000000d6>; clock-names =3D "pwm", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000d9>; #pwm-cells =3D <0x00000003>; status =3D "disabled"; phandle =3D <0x0000002e>; }; pwm@ff1b0030 { compatible =3D "rockchip,rk3328-pwm"; reg =3D <0x00000000 0xff1b0030 0x00000000 0x00000010>; interrupts =3D <0x00000000 0x00000032 0x00000004>; clocks =3D <0x0000004b 0x0000003c 0x0000004b = 0x000000d6>; clock-names =3D "pwm", "pclk"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000da>; #pwm-cells =3D <0x00000003>; status =3D "disabled"; phandle =3D <0x0000002f>; }; thermal-zones { soc-thermal { polling-delay-passive =3D <0x00000014>; polling-delay =3D <0x000003e8>; sustainable-power =3D <0x000003e8>; thermal-sensors =3D <0x00000034 0x00000000>; phandle =3D <0x00000030>; trips { trip-point0 { temperature =3D <0x00011170>; hysteresis =3D <0x000007d0>; type =3D "passive"; phandle =3D <0x00000031>; }; trip-point1 { temperature =3D <0x00014c08>; hysteresis =3D <0x000007d0>; type =3D "passive"; phandle =3D <0x00000032>; }; soc-crit { temperature =3D <0x00017318>; hysteresis =3D <0x000007d0>; type =3D "critical"; phandle =3D <0x00000033>; }; }; cooling-maps { map0 { trip =3D <0x00000032>; cooling-device =3D <0x00000001 = 0xffffffff 0xffffffff 0x00000002 0xffffffff 0xffffffff 0x00000003 = 0xffffffff 0xffffffff 0x00000004 0xffffffff 0xffffffff>; contribution =3D <0x00001000>; }; }; }; }; tsadc@ff250000 { compatible =3D "rockchip,rk3328-tsadc"; reg =3D <0x00000000 0xff250000 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x0000003a 0x00000004>; assigned-clocks =3D <0x0000004b 0x00000024>; assigned-clock-rates =3D <0x0000c350>; clocks =3D <0x0000004b 0x00000024 0x0000004b = 0x000000d5>; clock-names =3D "tsadc", "apb_pclk"; pinctrl-names =3D "init", "default", "sleep"; pinctrl-0 =3D <0x00000081>; pinctrl-1 =3D <0x00000082>; pinctrl-2 =3D <0x00000081>; resets =3D <0x0000004b 0x00000042>; reset-names =3D "tsadc-apb"; rockchip,grf =3D <0x00000017>; rockchip,hw-tshut-temp =3D <0x000186a0>; #thermal-sensor-cells =3D <0x00000001>; status =3D "okay"; rockchip,hw-tshut-mode =3D <0x00000000>; rockchip,hw-tshut-polarity =3D <0x00000000>; phandle =3D <0x00000034>; }; efuse@ff260000 { compatible =3D "rockchip,rk3328-efuse"; reg =3D <0x00000000 0xff260000 0x00000000 0x00000050>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000001>; clocks =3D <0x0000004b 0x0000003e>; clock-names =3D "pclk_efuse"; rockchip,efuse-size =3D <0x00000020>; phandle =3D <0x00000035>; id@7 { reg =3D <0x00000007 0x00000010>; phandle =3D <0x00000036>; }; cpu-leakage@17 { reg =3D <0x00000017 0x00000001>; phandle =3D <0x00000037>; }; logic-leakage@19 { reg =3D <0x00000019 0x00000001>; phandle =3D <0x00000038>; }; cpu-version@1a { reg =3D <0x0000001a 0x00000001>; bits =3D <0x00000003 0x00000003>; phandle =3D <0x00000039>; }; }; adc@ff280000 { compatible =3D "rockchip,rk3328-saradc", = "rockchip,rk3399-saradc"; reg =3D <0x00000000 0xff280000 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000050 0x00000004>; #io-channel-cells =3D <0x00000001>; clocks =3D <0x0000004b 0x00000025 0x0000004b = 0x000000ea>; clock-names =3D "saradc", "apb_pclk"; resets =3D <0x0000004b 0x00000056>; reset-names =3D "saradc-apb"; status =3D "disabled"; phandle =3D <0x0000003a>; }; gpu@ff300000 { compatible =3D "rockchip,rk3328-mali", "arm,mali-450"; reg =3D <0x00000000 0xff300000 0x00000000 0x00040000>; interrupts =3D * 0x00000000080f33a0 [0x00000054]; interrupt-names =3D "gp", "gpmmu", "pp", "pp0", = "ppmmu0", "pp1", "ppmmu1"; clocks =3D <0x0000004b 0x00000087 0x0000004b = 0x00000087>; clock-names =3D "bus", "core"; resets =3D <0x0000004b 0x00000066>; phandle =3D <0x0000003b>; }; iommu@ff330200 { compatible =3D "rockchip,iommu"; reg =3D <0x00000000 0xff330200 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000060 0x00000004>; interrupt-names =3D "h265e_mmu"; clocks =3D <0x0000004b 0x00000093 0x0000004b = 0x000000dd>; clock-names =3D "aclk", "iface"; #iommu-cells =3D <0x00000000>; status =3D "disabled"; phandle =3D <0x0000003c>; }; iommu@ff340800 { compatible =3D "rockchip,iommu"; reg =3D <0x00000000 0xff340800 0x00000000 0x00000040>; interrupts =3D <0x00000000 0x00000062 0x00000004>; interrupt-names =3D "vepu_mmu"; clocks =3D <0x0000004b 0x0000008f 0x0000004b = 0x00000146>; clock-names =3D "aclk", "iface"; #iommu-cells =3D <0x00000000>; status =3D "disabled"; phandle =3D <0x0000003d>; }; video-codec@ff350000 { compatible =3D "rockchip,rk3328-vpu"; reg =3D <0x00000000 0xff350000 0x00000000 0x00000800>; interrupts =3D <0x00000000 0x00000009 0x00000004>; interrupt-names =3D "vdpu"; clocks =3D <0x0000004b 0x0000008f 0x0000004b = 0x00000146>; clock-names =3D "aclk", "hclk"; iommus =3D <0x0000003f>; power-domains =3D <0x0000001a 0x00000008>; phandle =3D <0x0000003e>; }; iommu@ff350800 { compatible =3D "rockchip,iommu"; reg =3D <0x00000000 0xff350800 0x00000000 0x00000040>; interrupts =3D <0x00000000 0x0000000b 0x00000004>; interrupt-names =3D "vpu_mmu"; clocks =3D <0x0000004b 0x0000008f 0x0000004b = 0x00000146>; clock-names =3D "aclk", "iface"; #iommu-cells =3D <0x00000000>; power-domains =3D <0x0000001a 0x00000008>; phandle =3D <0x0000003f>; }; iommu@ff360480 { compatible =3D "rockchip,iommu"; reg =3D <0x00000000 0xff360480 0x00000000 0x00000040 = 0x00000000 0xff3604c0 0x00000000 0x00000040>; interrupts =3D <0x00000000 0x0000004a 0x00000004>; interrupt-names =3D "rkvdec_mmu"; clocks =3D <0x0000004b 0x0000008b 0x0000004b = 0x00000142>; clock-names =3D "aclk", "iface"; #iommu-cells =3D <0x00000000>; status =3D "disabled"; phandle =3D <0x00000040>; }; vop@ff370000 { compatible =3D "rockchip,rk3328-vop"; reg =3D <0x00000000 0xff370000 0x00000000 0x00003efc>; interrupts =3D <0x00000000 0x00000020 0x00000004>; clocks =3D <0x0000004b 0x00000091 0x0000004b 0x00000078 = 0x0000004b 0x0000013b>; clock-names =3D "aclk_vop", "dclk_vop", "hclk_vop"; resets =3D <0x0000004b 0x00000085 0x0000004b 0x00000086 = 0x0000004b 0x00000087>; reset-names =3D "axi", "ahb", "dclk"; iommus =3D <0x00000044>; status =3D "okay"; phandle =3D <0x00000041>; port { #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; phandle =3D <0x00000042>; endpoint@0 { reg =3D <0x00000000>; remote-endpoint =3D <0x00000047>; phandle =3D <0x00000043>; }; }; }; iommu@ff373f00 { compatible =3D "rockchip,iommu"; reg =3D <0x00000000 0xff373f00 0x00000000 0x00000100>; interrupts =3D <0x00000000 0x00000020 0x00000004>; interrupt-names =3D "vop_mmu"; clocks =3D <0x0000004b 0x00000091 0x0000004b = 0x0000013b>; clock-names =3D "aclk", "iface"; #iommu-cells =3D <0x00000000>; status =3D "okay"; phandle =3D <0x00000044>; }; hdmi@ff3c0000 { compatible =3D "rockchip,rk3328-dw-hdmi"; reg =3D <0x00000000 0xff3c0000 0x00000000 0x00020000>; reg-io-width =3D <0x00000004>; interrupts =3D <0x00000000 0x00000023 0x00000004 = 0x00000000 0x00000047 0x00000004>; clocks =3D <0x0000004b 0x000000e7 0x0000004b 0x00000046 = 0x0000004b 0x0000001e>; clock-names =3D "iahb", "isfr", "cec"; phys =3D <0x0000004a>; phy-names =3D "hdmi"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000e4 0x00000074 0x000000e5>; rockchip,grf =3D <0x00000017>; #sound-dai-cells =3D <0x00000000>; status =3D "okay"; phandle =3D <0x00000045>; ports { port { phandle =3D <0x00000046>; endpoint { remote-endpoint =3D = <0x00000043>; phandle =3D <0x00000047>; }; }; }; }; codec@ff410000 { compatible =3D "rockchip,rk3328-codec"; reg =3D <0x00000000 0xff410000 0x00000000 0x00001000>; clocks =3D <0x0000004b 0x000000eb 0x0000004b = 0x0000002a>; clock-names =3D "pclk", "mclk"; rockchip,grf =3D <0x00000017>; #sound-dai-cells =3D <0x00000000>; status =3D "okay"; mute-gpios =3D <0x00000019 0x00000000 0x00000001>; phandle =3D <0x00000048>; port@0 { endpoint { remote-endpoint =3D <0x00000011>; phandle =3D <0x00000049>; }; }; }; phy@ff430000 { compatible =3D "rockchip,rk3328-hdmi-phy"; reg =3D <0x00000000 0xff430000 0x00000000 0x00010000>; interrupts =3D <0x00000000 0x00000053 0x00000004>; clocks =3D <0x0000004b 0x000000e4 0x0000000d 0x0000004b = 0x00000079>; clock-names =3D "sysclk", "refoclk", "refpclk"; clock-output-names =3D "hdmi_phy"; #clock-cells =3D <0x00000000>; nvmem-cells =3D <0x00000039>; nvmem-cell-names =3D "cpu-version"; #phy-cells =3D <0x00000000>; status =3D "okay"; phandle =3D <0x0000004a>; }; clock-controller@ff440000 { compatible =3D "rockchip,rk3328-cru", "rockchip,cru", = "syscon"; reg =3D <0x00000000 0xff440000 0x00000000 0x00001000>; rockchip,grf =3D <0x00000017>; #clock-cells =3D <0x00000001>; #reset-cells =3D <0x00000001>; assigned-clocks =3D * 0x00000000080f4094 [0x000000f8]; assigned-clock-parents =3D <0x0000004b 0x0000007a = 0x0000004b 0x00000001 0x0000004b 0x00000004 0x0000000d 0x0000000d = 0x0000000d>; assigned-clock-rates =3D * 0x00000000080f41c8 = [0x0000007c]; phandle =3D <0x0000004b>; }; syscon@ff450000 { compatible =3D "rockchip,rk3328-usb2phy-grf", "syscon", = "simple-mfd"; reg =3D <0x00000000 0xff450000 0x00000000 0x00010000>; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000001>; phandle =3D <0x0000004c>; usb2-phy@100 { compatible =3D "rockchip,rk3328-usb2phy"; reg =3D <0x00000100 0x00000010>; clocks =3D <0x0000000d>; clock-names =3D "phyclk"; clock-output-names =3D "usb480m_phy"; #clock-cells =3D <0x00000000>; assigned-clocks =3D <0x0000004b 0x0000007b>; assigned-clock-parents =3D <0x0000004d>; status =3D "okay"; phandle =3D <0x0000004d>; otg-port { #phy-cells =3D <0x00000000>; interrupts =3D <0x00000000 0x0000003b = 0x00000004 0x00000000 0x0000003c 0x00000004 0x00000000 0x0000003d = 0x00000004>; interrupt-names =3D "otg-bvalid", = "otg-id", "linestate"; status =3D "okay"; phandle =3D <0x0000004e>; }; host-port { #phy-cells =3D <0x00000000>; interrupts =3D <0x00000000 0x0000003e = 0x00000004>; interrupt-names =3D "linestate"; status =3D "okay"; phandle =3D <0x0000004f>; }; }; }; mmc@ff500000 { compatible =3D "rockchip,rk3328-dw-mshc", = "rockchip,rk3288-dw-mshc"; reg =3D <0x00000000 0xff500000 0x00000000 0x00004000>; interrupts =3D <0x00000000 0x0000000c 0x00000004>; clocks =3D <0x0000004b 0x0000013d 0x0000004b 0x00000021 = 0x0000004b 0x0000004a 0x0000004b 0x0000004e>; clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth =3D <0x00000100>; max-frequency =3D <0x08f0d180>; status =3D "okay"; bus-width =3D <0x00000004>; cap-mmc-highspeed; cap-sd-highspeed; disable-wp; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000ba 0x000000bb 0x000000bc = 0x000000bf>; vmmc-supply =3D <0x000000ec>; phandle =3D <0x00000050>; }; mmc@ff510000 { compatible =3D "rockchip,rk3328-dw-mshc", = "rockchip,rk3288-dw-mshc"; reg =3D <0x00000000 0xff510000 0x00000000 0x00004000>; interrupts =3D <0x00000000 0x0000000d 0x00000004>; clocks =3D <0x0000004b 0x0000013e 0x0000004b 0x00000022 = 0x0000004b 0x0000004b 0x0000004b 0x0000004f>; clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth =3D <0x00000100>; max-frequency =3D <0x08f0d180>; status =3D "disabled"; phandle =3D <0x00000051>; }; mmc@ff520000 { compatible =3D "rockchip,rk3328-dw-mshc", = "rockchip,rk3288-dw-mshc"; reg =3D <0x00000000 0xff520000 0x00000000 0x00004000>; interrupts =3D <0x00000000 0x0000000e 0x00000004>; clocks =3D <0x0000004b 0x0000013f 0x0000004b 0x00000023 = 0x0000004b 0x0000004c 0x0000004b 0x00000050>; clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth =3D <0x00000100>; max-frequency =3D <0x08f0d180>; status =3D "okay"; bus-width =3D <0x00000008>; cap-mmc-highspeed; mmc-hs200-1_8v; non-removable; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000d0 0x000000d1 0x000000d6>; vmmc-supply =3D <0x00000024>; vqmmc-supply =3D <0x00000026>; phandle =3D <0x00000052>; }; ethernet@ff540000 { local-mac-address =3D [aa de e4 1b 49 c8]; compatible =3D "rockchip,rk3328-gmac"; reg =3D <0x00000000 0xff540000 0x00000000 0x00010000>; interrupts =3D <0x00000000 0x00000018 0x00000004>; interrupt-names =3D "macirq"; clocks =3D <0x0000004b 0x00000064 0x0000004b 0x00000057 = 0x0000004b 0x00000058 0x0000004b 0x0000005a 0x0000004b 0x00000059 = 0x0000004b 0x00000096 0x0000004b 0x000000df>; clock-names =3D "stmmaceth", "mac_clk_rx", "mac_clk_tx", = "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; resets =3D <0x0000004b 0x00000063>; reset-names =3D "stmmaceth"; rockchip,grf =3D <0x00000017>; snps,txpbl =3D <0x00000004>; status =3D "okay"; assigned-clocks =3D <0x0000004b 0x00000064 0x0000004b = 0x00000066>; assigned-clock-parents =3D <0x000000eb 0x000000eb>; clock_in_out =3D "input"; phy-supply =3D <0x00000024>; phy-mode =3D "rgmii"; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000db>; snps,force_thresh_dma_mode; snps,reset-gpio =3D <0x0000005c 0x00000012 0x00000001>; snps,reset-active-low; snps,reset-delays-us =3D <0x00000000 0x00002710 = 0x0000c350>; tx_delay =3D <0x00000024>; rx_delay =3D <0x00000018>; phandle =3D <0x00000053>; }; ethernet@ff550000 { compatible =3D "rockchip,rk3328-gmac"; reg =3D <0x00000000 0xff550000 0x00000000 0x00010000>; rockchip,grf =3D <0x00000017>; interrupts =3D <0x00000000 0x00000015 0x00000004>; interrupt-names =3D "macirq"; clocks =3D <0x0000004b 0x00000054 0x0000004b 0x00000053 = 0x0000004b 0x00000053 0x0000004b 0x00000055 0x0000004b 0x00000095 = 0x0000004b 0x000000de 0x0000004b 0x00000056>; clock-names =3D "stmmaceth", "mac_clk_rx", "mac_clk_tx", = "clk_mac_ref", "aclk_mac", "pclk_mac", "clk_macphy"; resets =3D <0x0000004b 0x00000062 0x0000004b = 0x00000064>; reset-names =3D "stmmaceth", "mac-phy"; phy-mode =3D "rmii"; phy-handle =3D <0x00000055>; snps,txpbl =3D <0x00000004>; status =3D "disabled"; phandle =3D <0x00000054>; mdio { compatible =3D "snps,dwmac-mdio"; #address-cells =3D <0x00000001>; #size-cells =3D <0x00000000>; phy@0 { compatible =3D = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; reg =3D <0x00000000>; clocks =3D <0x0000004b 0x00000056>; resets =3D <0x0000004b 0x00000064>; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000df 0x000000e1>; phy-is-integrated; phandle =3D <0x00000055>; }; }; }; usb@ff580000 { compatible =3D "rockchip,rk3328-usb", = "rockchip,rk3066-usb", "snps,dwc2"; reg =3D <0x00000000 0xff580000 0x00000000 0x00040000>; interrupts =3D <0x00000000 0x00000017 0x00000004>; clocks =3D <0x0000004b 0x0000014d>; clock-names =3D "otg"; dr_mode =3D "host"; g-np-tx-fifo-size =3D <0x00000010>; g-rx-fifo-size =3D <0x00000118>; g-tx-fifo-size =3D <0x00000100 0x00000080 0x00000080 = 0x00000040 0x00000020 0x00000010>; phys =3D <0x0000004e>; phy-names =3D "usb2-phy"; status =3D "okay"; phandle =3D <0x00000056>; }; usb@ff5c0000 { compatible =3D "generic-ehci"; reg =3D <0x00000000 0xff5c0000 0x00000000 0x00010000>; interrupts =3D <0x00000000 0x00000010 0x00000004>; clocks =3D <0x0000004b 0x0000014e 0x0000004d>; phys =3D <0x0000004f>; phy-names =3D "usb"; status =3D "okay"; phandle =3D <0x00000057>; }; usb@ff5d0000 { compatible =3D "generic-ohci"; reg =3D <0x00000000 0xff5d0000 0x00000000 0x00010000>; interrupts =3D <0x00000000 0x00000011 0x00000004>; clocks =3D <0x0000004b 0x0000014e 0x0000004d>; phys =3D <0x0000004f>; phy-names =3D "usb"; status =3D "okay"; phandle =3D <0x00000058>; }; interrupt-controller@ff811000 { compatible =3D "arm,gic-400"; #interrupt-cells =3D <0x00000003>; #address-cells =3D <0x00000000>; interrupt-controller; reg =3D <0x00000000 0xff811000 0x00000000 0x00001000 = 0x00000000 0xff812000 0x00000000 0x00002000 0x00000000 0xff814000 = 0x00000000 0x00002000 0x00000000 0xff816000 0x00000000 0x00002000>; interrupts =3D <0x00000001 0x00000009 0x00000f04>; phandle =3D <0x00000059>; }; pinctrl { compatible =3D "rockchip,rk3328-pinctrl"; rockchip,grf =3D <0x00000017>; #address-cells =3D <0x00000002>; #size-cells =3D <0x00000002>; ranges; phandle =3D <0x0000005a>; gpio0@ff210000 { compatible =3D "rockchip,gpio-bank"; reg =3D <0x00000000 0xff210000 0x00000000 = 0x00000100>; interrupts =3D <0x00000000 0x00000033 = 0x00000004>; clocks =3D <0x0000004b 0x000000c8>; gpio-controller; #gpio-cells =3D <0x00000002>; interrupt-controller; #interrupt-cells =3D <0x00000002>; phandle =3D <0x0000005b>; }; gpio1@ff220000 { compatible =3D "rockchip,gpio-bank"; reg =3D <0x00000000 0xff220000 0x00000000 = 0x00000100>; interrupts =3D <0x00000000 0x00000034 = 0x00000004>; clocks =3D <0x0000004b 0x000000c9>; gpio-controller; #gpio-cells =3D <0x00000002>; interrupt-controller; #interrupt-cells =3D <0x00000002>; phandle =3D <0x0000005c>; }; gpio2@ff230000 { compatible =3D "rockchip,gpio-bank"; reg =3D <0x00000000 0xff230000 0x00000000 = 0x00000100>; interrupts =3D <0x00000000 0x00000035 = 0x00000004>; clocks =3D <0x0000004b 0x000000ca>; gpio-controller; #gpio-cells =3D <0x00000002>; interrupt-controller; #interrupt-cells =3D <0x00000002>; phandle =3D <0x0000005d>; }; gpio3@ff240000 { compatible =3D "rockchip,gpio-bank"; reg =3D <0x00000000 0xff240000 0x00000000 = 0x00000100>; interrupts =3D <0x00000000 0x00000036 = 0x00000004>; clocks =3D <0x0000004b 0x000000cb>; gpio-controller; #gpio-cells =3D <0x00000002>; interrupt-controller; #interrupt-cells =3D <0x00000002>; phandle =3D <0x0000005e>; }; pcfg-pull-up { bias-pull-up; phandle =3D <0x0000005f>; }; pcfg-pull-down { bias-pull-down; phandle =3D <0x00000060>; }; pcfg-pull-none { bias-disable; phandle =3D <0x00000061>; }; pcfg-pull-none-2ma { bias-disable; drive-strength =3D <0x00000002>; phandle =3D <0x00000062>; }; pcfg-pull-up-2ma { bias-pull-up; drive-strength =3D <0x00000002>; phandle =3D <0x00000063>; }; pcfg-pull-up-4ma { bias-pull-up; drive-strength =3D <0x00000004>; phandle =3D <0x00000064>; }; pcfg-pull-none-4ma { bias-disable; drive-strength =3D <0x00000004>; phandle =3D <0x00000065>; }; pcfg-pull-down-4ma { bias-pull-down; drive-strength =3D <0x00000004>; phandle =3D <0x00000066>; }; pcfg-pull-none-8ma { bias-disable; drive-strength =3D <0x00000008>; phandle =3D <0x00000067>; }; pcfg-pull-up-8ma { bias-pull-up; drive-strength =3D <0x00000008>; phandle =3D <0x00000068>; }; pcfg-pull-none-12ma { bias-disable; drive-strength =3D <0x0000000c>; phandle =3D <0x00000069>; }; pcfg-pull-up-12ma { bias-pull-up; drive-strength =3D <0x0000000c>; phandle =3D <0x0000006a>; }; pcfg-output-high { output-high; phandle =3D <0x0000006b>; }; pcfg-output-low { output-low; phandle =3D <0x0000006c>; }; pcfg-input-high { bias-pull-up; input-enable; phandle =3D <0x0000006d>; }; pcfg-input { input-enable; phandle =3D <0x0000006e>; }; i2c0 { i2c0-xfer { rockchip,pins =3D <0x00000002 0x00000018 = 0x00000001 0x00000061 0x00000002 0x00000019 0x00000001 0x00000061>; phandle =3D <0x0000006f>; }; }; i2c1 { i2c1-xfer { rockchip,pins =3D <0x00000002 0x00000004 = 0x00000002 0x00000061 0x00000002 0x00000005 0x00000002 0x00000061>; phandle =3D <0x00000070>; }; }; i2c2 { i2c2-xfer { rockchip,pins =3D <0x00000002 0x0000000d = 0x00000001 0x00000061 0x00000002 0x0000000e 0x00000001 0x00000061>; phandle =3D <0x00000071>; }; }; i2c3 { i2c3-xfer { rockchip,pins =3D <0x00000000 0x00000005 = 0x00000002 0x00000061 0x00000000 0x00000006 0x00000002 0x00000061>; phandle =3D <0x00000072>; }; i2c3-gpio { rockchip,pins =3D <0x00000000 0x00000005 = 0x00000000 0x00000061 0x00000000 0x00000006 0x00000000 0x00000061>; phandle =3D <0x00000073>; }; }; hdmi_i2c { hdmii2c-xfer { rockchip,pins =3D <0x00000000 0x00000005 = 0x00000001 0x00000061 0x00000000 0x00000006 0x00000001 0x00000061>; phandle =3D <0x00000074>; }; }; pdm-0 { pdmm0-clk { rockchip,pins =3D <0x00000002 0x00000012 = 0x00000002 0x00000061>; phandle =3D <0x00000075>; }; pdmm0-fsync { rockchip,pins =3D <0x00000002 0x00000017 = 0x00000002 0x00000061>; phandle =3D <0x00000076>; }; pdmm0-sdi0 { rockchip,pins =3D <0x00000002 0x00000013 = 0x00000002 0x00000061>; phandle =3D <0x00000077>; }; pdmm0-sdi1 { rockchip,pins =3D <0x00000002 0x00000014 = 0x00000002 0x00000061>; phandle =3D <0x00000078>; }; pdmm0-sdi2 { rockchip,pins =3D <0x00000002 0x00000015 = 0x00000002 0x00000061>; phandle =3D <0x00000079>; }; pdmm0-sdi3 { rockchip,pins =3D <0x00000002 0x00000016 = 0x00000002 0x00000061>; phandle =3D <0x0000007a>; }; pdmm0-clk-sleep { rockchip,pins =3D <0x00000002 0x00000012 = 0x00000000 0x0000006d>; phandle =3D <0x0000007b>; }; pdmm0-sdi0-sleep { rockchip,pins =3D <0x00000002 0x00000013 = 0x00000000 0x0000006d>; phandle =3D <0x0000007c>; }; pdmm0-sdi1-sleep { rockchip,pins =3D <0x00000002 0x00000014 = 0x00000000 0x0000006d>; phandle =3D <0x0000007d>; }; pdmm0-sdi2-sleep { rockchip,pins =3D <0x00000002 0x00000015 = 0x00000000 0x0000006d>; phandle =3D <0x0000007e>; }; pdmm0-sdi3-sleep { rockchip,pins =3D <0x00000002 0x00000016 = 0x00000000 0x0000006d>; phandle =3D <0x0000007f>; }; pdmm0-fsync-sleep { rockchip,pins =3D <0x00000002 0x00000017 = 0x00000000 0x0000006d>; phandle =3D <0x00000080>; }; }; tsadc { otp-gpio { rockchip,pins =3D <0x00000002 0x0000000d = 0x00000000 0x00000061>; phandle =3D <0x00000081>; }; otp-out { rockchip,pins =3D <0x00000002 0x0000000d = 0x00000001 0x00000061>; phandle =3D <0x00000082>; }; }; uart0 { uart0-xfer { rockchip,pins =3D <0x00000001 0x00000009 = 0x00000001 0x0000005f 0x00000001 0x00000008 0x00000001 0x00000061>; phandle =3D <0x00000083>; }; uart0-cts { rockchip,pins =3D <0x00000001 0x0000000b = 0x00000001 0x00000061>; phandle =3D <0x00000084>; }; uart0-rts { rockchip,pins =3D <0x00000001 0x0000000a = 0x00000001 0x00000061>; phandle =3D <0x00000085>; }; uart0-rts-gpio { rockchip,pins =3D <0x00000001 0x0000000a = 0x00000000 0x00000061>; phandle =3D <0x00000086>; }; }; uart1 { uart1-xfer { rockchip,pins =3D <0x00000003 0x00000004 = 0x00000004 0x0000005f 0x00000003 0x00000006 0x00000004 0x00000061>; phandle =3D <0x00000087>; }; uart1-cts { rockchip,pins =3D <0x00000003 0x00000007 = 0x00000004 0x00000061>; phandle =3D <0x00000088>; }; uart1-rts { rockchip,pins =3D <0x00000003 0x00000005 = 0x00000004 0x00000061>; phandle =3D <0x00000089>; }; uart1-rts-gpio { rockchip,pins =3D <0x00000003 0x00000005 = 0x00000000 0x00000061>; phandle =3D <0x0000008a>; }; }; uart2-0 { uart2m0-xfer { rockchip,pins =3D <0x00000001 0x00000000 = 0x00000002 0x0000005f 0x00000001 0x00000001 0x00000002 0x00000061>; phandle =3D <0x0000008b>; }; }; uart2-1 { uart2m1-xfer { rockchip,pins =3D <0x00000002 0x00000000 = 0x00000001 0x0000005f 0x00000002 0x00000001 0x00000001 0x00000061>; phandle =3D <0x0000008c>; }; }; spi0-0 { spi0m0-clk { rockchip,pins =3D <0x00000002 0x00000008 = 0x00000001 0x0000005f>; phandle =3D <0x0000008d>; }; spi0m0-cs0 { rockchip,pins =3D <0x00000002 0x0000000b = 0x00000001 0x0000005f>; phandle =3D <0x0000008e>; }; spi0m0-tx { rockchip,pins =3D <0x00000002 0x00000009 = 0x00000001 0x0000005f>; phandle =3D <0x0000008f>; }; spi0m0-rx { rockchip,pins =3D <0x00000002 0x0000000a = 0x00000001 0x0000005f>; phandle =3D <0x00000090>; }; spi0m0-cs1 { rockchip,pins =3D <0x00000002 0x0000000c = 0x00000001 0x0000005f>; phandle =3D <0x00000091>; }; }; spi0-1 { spi0m1-clk { rockchip,pins =3D <0x00000003 0x00000017 = 0x00000002 0x0000005f>; phandle =3D <0x00000092>; }; spi0m1-cs0 { rockchip,pins =3D <0x00000003 0x0000001a = 0x00000002 0x0000005f>; phandle =3D <0x00000093>; }; spi0m1-tx { rockchip,pins =3D <0x00000003 0x00000019 = 0x00000002 0x0000005f>; phandle =3D <0x00000094>; }; spi0m1-rx { rockchip,pins =3D <0x00000003 0x00000018 = 0x00000002 0x0000005f>; phandle =3D <0x00000095>; }; spi0m1-cs1 { rockchip,pins =3D <0x00000003 0x0000001b = 0x00000002 0x0000005f>; phandle =3D <0x00000096>; }; }; spi0-2 { spi0m2-clk { rockchip,pins =3D <0x00000003 0x00000000 = 0x00000004 0x0000005f>; phandle =3D <0x00000097>; }; spi0m2-cs0 { rockchip,pins =3D <0x00000003 0x00000008 = 0x00000003 0x0000005f>; phandle =3D <0x00000098>; }; spi0m2-tx { rockchip,pins =3D <0x00000003 0x00000001 = 0x00000004 0x0000005f>; phandle =3D <0x00000099>; }; spi0m2-rx { rockchip,pins =3D <0x00000003 0x00000002 = 0x00000004 0x0000005f>; phandle =3D <0x0000009a>; }; }; i2s1 { i2s1-mclk { rockchip,pins =3D <0x00000002 0x0000000f = 0x00000001 0x00000061>; phandle =3D <0x0000009b>; }; i2s1-sclk { rockchip,pins =3D <0x00000002 0x00000012 = 0x00000001 0x00000061>; phandle =3D <0x0000009c>; }; i2s1-lrckrx { rockchip,pins =3D <0x00000002 0x00000010 = 0x00000001 0x00000061>; phandle =3D <0x0000009d>; }; i2s1-lrcktx { rockchip,pins =3D <0x00000002 0x00000011 = 0x00000001 0x00000061>; phandle =3D <0x0000009e>; }; i2s1-sdi { rockchip,pins =3D <0x00000002 0x00000013 = 0x00000001 0x00000061>; phandle =3D <0x0000009f>; }; i2s1-sdo { rockchip,pins =3D <0x00000002 0x00000017 = 0x00000001 0x00000061>; phandle =3D <0x000000a0>; }; i2s1-sdio1 { rockchip,pins =3D <0x00000002 0x00000014 = 0x00000001 0x00000061>; phandle =3D <0x000000a1>; }; i2s1-sdio2 { rockchip,pins =3D <0x00000002 0x00000015 = 0x00000001 0x00000061>; phandle =3D <0x000000a2>; }; i2s1-sdio3 { rockchip,pins =3D <0x00000002 0x00000016 = 0x00000001 0x00000061>; phandle =3D <0x000000a3>; }; i2s1-sleep { rockchip,pins =3D * 0x00000000080f695c = [0x00000090]; phandle =3D <0x000000a4>; }; }; i2s2-0 { i2s2m0-mclk { rockchip,pins =3D <0x00000001 0x00000015 = 0x00000001 0x00000061>; phandle =3D <0x000000a5>; }; i2s2m0-sclk { rockchip,pins =3D <0x00000001 0x00000016 = 0x00000001 0x00000061>; phandle =3D <0x000000a6>; }; i2s2m0-lrckrx { rockchip,pins =3D <0x00000001 0x0000001a = 0x00000001 0x00000061>; phandle =3D <0x000000a7>; }; i2s2m0-lrcktx { rockchip,pins =3D <0x00000001 0x00000017 = 0x00000001 0x00000061>; phandle =3D <0x000000a8>; }; i2s2m0-sdi { rockchip,pins =3D <0x00000001 0x00000018 = 0x00000001 0x00000061>; phandle =3D <0x000000a9>; }; i2s2m0-sdo { rockchip,pins =3D <0x00000001 0x00000019 = 0x00000001 0x00000061>; phandle =3D <0x000000aa>; }; i2s2m0-sleep { rockchip,pins =3D * 0x00000000080f6bb8 = [0x00000060]; phandle =3D <0x000000ab>; }; }; i2s2-1 { i2s2m1-mclk { rockchip,pins =3D <0x00000001 0x00000015 = 0x00000001 0x00000061>; phandle =3D <0x000000ac>; }; i2s2m1-sclk { rockchip,pins =3D <0x00000003 0x00000000 = 0x00000006 0x00000061>; phandle =3D <0x000000ad>; }; i2sm1-lrckrx { rockchip,pins =3D <0x00000003 0x00000008 = 0x00000006 0x00000061>; phandle =3D <0x000000ae>; }; i2s2m1-lrcktx { rockchip,pins =3D <0x00000003 0x00000008 = 0x00000004 0x00000061>; phandle =3D <0x000000af>; }; i2s2m1-sdi { rockchip,pins =3D <0x00000003 0x00000002 = 0x00000006 0x00000061>; phandle =3D <0x000000b0>; }; i2s2m1-sdo { rockchip,pins =3D <0x00000003 0x00000001 = 0x00000006 0x00000061>; phandle =3D <0x000000b1>; }; i2s2m1-sleep { rockchip,pins =3D * 0x00000000080f6de4 = [0x00000050]; phandle =3D <0x000000b2>; }; }; spdif-0 { spdifm0-tx { rockchip,pins =3D <0x00000000 0x0000001b = 0x00000001 0x00000061>; phandle =3D <0x000000b3>; }; }; spdif-1 { spdifm1-tx { rockchip,pins =3D <0x00000002 0x00000011 = 0x00000002 0x00000061>; phandle =3D <0x000000b4>; }; }; spdif-2 { spdifm2-tx { rockchip,pins =3D <0x00000000 0x00000002 = 0x00000002 0x00000061>; phandle =3D <0x000000b5>; }; }; sdmmc0-0 { sdmmc0m0-pwren { rockchip,pins =3D <0x00000002 0x00000007 = 0x00000001 0x00000064>; phandle =3D <0x000000b6>; }; sdmmc0m0-gpio { rockchip,pins =3D <0x00000002 0x00000007 = 0x00000000 0x00000064>; phandle =3D <0x000000b7>; }; }; sdmmc0-1 { sdmmc0m1-pwren { rockchip,pins =3D <0x00000000 0x0000001e = 0x00000003 0x00000064>; phandle =3D <0x000000b8>; }; sdmmc0m1-gpio { rockchip,pins =3D <0x00000000 0x0000001e = 0x00000000 0x00000064>; phandle =3D <0x000000b9>; }; }; sdmmc0 { sdmmc0-clk { rockchip,pins =3D <0x00000001 0x00000006 = 0x00000001 0x00000067>; phandle =3D <0x000000ba>; }; sdmmc0-cmd { rockchip,pins =3D <0x00000001 0x00000004 = 0x00000001 0x00000068>; phandle =3D <0x000000bb>; }; sdmmc0-dectn { rockchip,pins =3D <0x00000001 0x00000005 = 0x00000001 0x00000064>; phandle =3D <0x000000bc>; }; sdmmc0-wrprt { rockchip,pins =3D <0x00000001 0x00000007 = 0x00000001 0x00000064>; phandle =3D <0x000000bd>; }; sdmmc0-bus1 { rockchip,pins =3D <0x00000001 0x00000000 = 0x00000001 0x00000068>; phandle =3D <0x000000be>; }; sdmmc0-bus4 { rockchip,pins =3D <0x00000001 0x00000000 = 0x00000001 0x00000068 0x00000001 0x00000001 0x00000001 0x00000068 = 0x00000001 0x00000002 0x00000001 0x00000068 0x00000001 0x00000003 = 0x00000001 0x00000068>; phandle =3D <0x000000bf>; }; sdmmc0-gpio { rockchip,pins =3D * 0x00000000080f7254 = [0x00000080]; phandle =3D <0x000000c0>; }; }; sdmmc0ext { sdmmc0ext-clk { rockchip,pins =3D <0x00000003 0x00000002 = 0x00000003 0x00000065>; phandle =3D <0x000000c1>; }; sdmmc0ext-cmd { rockchip,pins =3D <0x00000003 0x00000000 = 0x00000003 0x00000064>; phandle =3D <0x000000c2>; }; sdmmc0ext-wrprt { rockchip,pins =3D <0x00000003 0x00000003 = 0x00000003 0x00000064>; phandle =3D <0x000000c3>; }; sdmmc0ext-dectn { rockchip,pins =3D <0x00000003 0x00000001 = 0x00000003 0x00000064>; phandle =3D <0x000000c4>; }; sdmmc0ext-bus1 { rockchip,pins =3D <0x00000003 0x00000004 = 0x00000003 0x00000064>; phandle =3D <0x000000c5>; }; sdmmc0ext-bus4 { rockchip,pins =3D <0x00000003 0x00000004 = 0x00000003 0x00000064 0x00000003 0x00000005 0x00000003 0x00000064 = 0x00000003 0x00000006 0x00000003 0x00000064 0x00000003 0x00000007 = 0x00000003 0x00000064>; phandle =3D <0x000000c6>; }; sdmmc0ext-gpio { rockchip,pins =3D * 0x00000000080f74e4 = [0x00000080]; phandle =3D <0x000000c7>; }; }; sdmmc1 { sdmmc1-clk { rockchip,pins =3D <0x00000001 0x0000000c = 0x00000001 0x00000067>; phandle =3D <0x000000c8>; }; sdmmc1-cmd { rockchip,pins =3D <0x00000001 0x0000000d = 0x00000001 0x00000068>; phandle =3D <0x000000c9>; }; sdmmc1-pwren { rockchip,pins =3D <0x00000001 0x00000012 = 0x00000001 0x00000068>; phandle =3D <0x000000ca>; }; sdmmc1-wrprt { rockchip,pins =3D <0x00000001 0x00000014 = 0x00000001 0x00000068>; phandle =3D <0x000000cb>; }; sdmmc1-dectn { rockchip,pins =3D <0x00000001 0x00000013 = 0x00000001 0x00000068>; phandle =3D <0x000000cc>; }; sdmmc1-bus1 { rockchip,pins =3D <0x00000001 0x0000000e = 0x00000001 0x00000068>; phandle =3D <0x000000cd>; }; sdmmc1-bus4 { rockchip,pins =3D <0x00000001 0x0000000e = 0x00000001 0x00000068 0x00000001 0x0000000f 0x00000001 0x00000068 = 0x00000001 0x00000010 0x00000001 0x00000068 0x00000001 0x00000011 = 0x00000001 0x00000068>; phandle =3D <0x000000ce>; }; sdmmc1-gpio { rockchip,pins =3D * 0x00000000080f77a0 = [0x00000090]; phandle =3D <0x000000cf>; }; }; emmc { emmc-clk { rockchip,pins =3D <0x00000003 0x00000015 = 0x00000002 0x00000069>; phandle =3D <0x000000d0>; }; emmc-cmd { rockchip,pins =3D <0x00000003 0x00000013 = 0x00000002 0x0000006a>; phandle =3D <0x000000d1>; }; emmc-pwren { rockchip,pins =3D <0x00000003 0x00000016 = 0x00000002 0x00000061>; phandle =3D <0x000000d2>; }; emmc-rstnout { rockchip,pins =3D <0x00000003 0x00000014 = 0x00000002 0x00000061>; phandle =3D <0x000000d3>; }; emmc-bus1 { rockchip,pins =3D <0x00000000 0x00000007 = 0x00000002 0x0000006a>; phandle =3D <0x000000d4>; }; emmc-bus4 { rockchip,pins =3D <0x00000000 0x00000007 = 0x00000002 0x0000006a 0x00000002 0x0000001c 0x00000002 0x0000006a = 0x00000002 0x0000001d 0x00000002 0x0000006a 0x00000002 0x0000001e = 0x00000002 0x0000006a>; phandle =3D <0x000000d5>; }; emmc-bus8 { rockchip,pins =3D * 0x00000000080f7a24 = [0x00000080]; phandle =3D <0x000000d6>; }; }; pwm0 { pwm0-pin { rockchip,pins =3D <0x00000002 0x00000004 = 0x00000001 0x00000061>; phandle =3D <0x000000d7>; }; }; pwm1 { pwm1-pin { rockchip,pins =3D <0x00000002 0x00000005 = 0x00000001 0x00000061>; phandle =3D <0x000000d8>; }; }; pwm2 { pwm2-pin { rockchip,pins =3D <0x00000002 0x00000006 = 0x00000001 0x00000061>; phandle =3D <0x000000d9>; }; }; pwmir { pwmir-pin { rockchip,pins =3D <0x00000002 0x00000002 = 0x00000001 0x00000061>; phandle =3D <0x000000da>; }; }; gmac-1 { rgmiim1-pins { rockchip,pins =3D * 0x00000000080f7c28 = [0x00000160]; phandle =3D <0x000000db>; }; rmiim1-pins { rockchip,pins =3D * 0x00000000080f7db8 = [0x00000100]; phandle =3D <0x000000dc>; }; }; gmac2phy { fephyled-speed10 { rockchip,pins =3D <0x00000000 0x0000001e = 0x00000001 0x00000061>; phandle =3D <0x000000dd>; }; fephyled-duplex { rockchip,pins =3D <0x00000000 0x0000001e = 0x00000002 0x00000061>; phandle =3D <0x000000de>; }; fephyled-rxm1 { rockchip,pins =3D <0x00000002 0x00000019 = 0x00000002 0x00000061>; phandle =3D <0x000000df>; }; fephyled-txm1 { rockchip,pins =3D <0x00000002 0x00000019 = 0x00000003 0x00000061>; phandle =3D <0x000000e0>; }; fephyled-linkm1 { rockchip,pins =3D <0x00000002 0x00000018 = 0x00000002 0x00000061>; phandle =3D <0x000000e1>; }; }; tsadc_pin { tsadc-int { rockchip,pins =3D <0x00000002 0x0000000d = 0x00000002 0x00000061>; phandle =3D <0x000000e2>; }; tsadc-gpio { rockchip,pins =3D <0x00000002 0x0000000d = 0x00000000 0x00000061>; phandle =3D <0x000000e3>; }; }; hdmi_pin { hdmi-cec { rockchip,pins =3D <0x00000000 0x00000003 = 0x00000001 0x00000061>; phandle =3D <0x000000e4>; }; hdmi-hpd { rockchip,pins =3D <0x00000000 0x00000004 = 0x00000001 0x00000060>; phandle =3D <0x000000e5>; }; }; cif-0 { dvp-d2d9-m0 { rockchip,pins =3D * 0x00000000080f818c = [0x000000c0]; phandle =3D <0x000000e6>; }; }; cif-1 { dvp-d2d9-m1 { rockchip,pins =3D * 0x00000000080f828c = [0x000000c0]; phandle =3D <0x000000e7>; }; }; ir { ir-int { rockchip,pins =3D <0x00000002 0x00000002 = 0x00000000 0x00000061>; phandle =3D <0x000000e8>; }; }; pmic { pmic-int-l { rockchip,pins =3D <0x00000002 0x00000006 = 0x00000000 0x0000005f>; phandle =3D <0x000000e9>; }; }; usb2 { usb20-host-drv { rockchip,pins =3D <0x00000000 0x00000002 = 0x00000000 0x00000061>; phandle =3D <0x000000ea>; }; }; }; chosen { stdout-path =3D "serial2:1500000n8"; }; external-gmac-clock { compatible =3D "fixed-clock"; clock-frequency =3D <0x07735940>; clock-output-names =3D "gmac_clkin"; #clock-cells =3D <0x00000000>; phandle =3D <0x000000eb>; }; sdmmc-regulator { compatible =3D "regulator-fixed"; gpio =3D <0x0000005b 0x0000001e 0x00000001>; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000b9>; regulator-name =3D "vcc_sd"; regulator-min-microvolt =3D <0x00325aa0>; regulator-max-microvolt =3D <0x00325aa0>; vin-supply =3D <0x00000024>; phandle =3D <0x000000ec>; }; vcc-host-5v-regulator { compatible =3D "regulator-fixed"; gpio =3D <0x0000005b 0x00000002 0x00000001>; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000ea>; regulator-name =3D "vcc_host_5v"; regulator-always-on; regulator-boot-on; vin-supply =3D <0x000000ef>; phandle =3D <0x000000ed>; }; vcc-host1-5v-regulator { compatible =3D "regulator-fixed"; gpio =3D <0x0000005b 0x00000002 0x00000001>; pinctrl-names =3D "default"; pinctrl-0 =3D <0x000000ea>; regulator-name =3D "vcc_host1_5v"; regulator-always-on; regulator-boot-on; vin-supply =3D <0x000000ef>; phandle =3D <0x000000ee>; }; vcc-sys { compatible =3D "regulator-fixed"; regulator-name =3D "vcc_sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <0x004c4b40>; regulator-max-microvolt =3D <0x004c4b40>; phandle =3D <0x000000ef>; }; ir-receiver { compatible =3D "gpio-ir-receiver"; gpios =3D <0x0000005d 0x00000002 0x00000001>; pinctrl-0 =3D <0x000000e8>; pinctrl-names =3D "default"; }; leds { compatible =3D "gpio-leds"; power { gpios =3D <0x00000020 0x00000001 0x00000001>; linux,default-trigger =3D "mmc0"; }; standby { gpios =3D <0x00000020 0x00000000 0x00000001>; linux,default-trigger =3D "heartbeat"; }; }; sound { compatible =3D "audio-graph-card"; label =3D "rockchip,rk3328"; dais =3D <0x00000010 0x00000014>; }; spdif-dit { compatible =3D "linux,spdif-dit"; #sound-dai-cells =3D <0x00000000>; port { endpoint { remote-endpoint =3D <0x00000015>; phandle =3D <0x000000f0>; }; }; }; __symbols__ { dit_p0_0 =3D "/spdif-dit/port/endpoint"; vcc_sys =3D "/vcc-sys"; vcc_otg_5v =3D "/vcc-host1-5v-regulator"; vcc_host1_5v =3D "/vcc-host1-5v-regulator"; vcc_host_5v =3D "/vcc-host-5v-regulator"; vcc_sd =3D "/sdmmc-regulator"; gmac_clkin =3D "/external-gmac-clock"; usb20_host_drv =3D "/pinctrl/usb2/usb20-host-drv"; pmic_int_l =3D "/pinctrl/pmic/pmic-int-l"; ir_int =3D "/pinctrl/ir/ir-int"; dvp_d2d9_m1 =3D "/pinctrl/cif-1/dvp-d2d9-m1"; dvp_d2d9_m0 =3D "/pinctrl/cif-0/dvp-d2d9-m0"; hdmi_hpd =3D "/pinctrl/hdmi_pin/hdmi-hpd"; hdmi_cec =3D "/pinctrl/hdmi_pin/hdmi-cec"; tsadc_gpio =3D "/pinctrl/tsadc_pin/tsadc-gpio"; tsadc_int =3D "/pinctrl/tsadc_pin/tsadc-int"; fephyled_linkm1 =3D "/pinctrl/gmac2phy/fephyled-linkm1"; fephyled_txm1 =3D "/pinctrl/gmac2phy/fephyled-txm1"; fephyled_rxm1 =3D "/pinctrl/gmac2phy/fephyled-rxm1"; fephyled_duplex =3D "/pinctrl/gmac2phy/fephyled-duplex"; fephyled_speed10 =3D = "/pinctrl/gmac2phy/fephyled-speed10"; rmiim1_pins =3D "/pinctrl/gmac-1/rmiim1-pins"; rgmiim1_pins =3D "/pinctrl/gmac-1/rgmiim1-pins"; pwmir_pin =3D "/pinctrl/pwmir/pwmir-pin"; pwm2_pin =3D "/pinctrl/pwm2/pwm2-pin"; pwm1_pin =3D "/pinctrl/pwm1/pwm1-pin"; pwm0_pin =3D "/pinctrl/pwm0/pwm0-pin"; emmc_bus8 =3D "/pinctrl/emmc/emmc-bus8"; emmc_bus4 =3D "/pinctrl/emmc/emmc-bus4"; emmc_bus1 =3D "/pinctrl/emmc/emmc-bus1"; emmc_rstnout =3D "/pinctrl/emmc/emmc-rstnout"; emmc_pwren =3D "/pinctrl/emmc/emmc-pwren"; emmc_cmd =3D "/pinctrl/emmc/emmc-cmd"; emmc_clk =3D "/pinctrl/emmc/emmc-clk"; sdmmc1_gpio =3D "/pinctrl/sdmmc1/sdmmc1-gpio"; sdmmc1_bus4 =3D "/pinctrl/sdmmc1/sdmmc1-bus4"; sdmmc1_bus1 =3D "/pinctrl/sdmmc1/sdmmc1-bus1"; sdmmc1_dectn =3D "/pinctrl/sdmmc1/sdmmc1-dectn"; sdmmc1_wrprt =3D "/pinctrl/sdmmc1/sdmmc1-wrprt"; sdmmc1_pwren =3D "/pinctrl/sdmmc1/sdmmc1-pwren"; sdmmc1_cmd =3D "/pinctrl/sdmmc1/sdmmc1-cmd"; sdmmc1_clk =3D "/pinctrl/sdmmc1/sdmmc1-clk"; sdmmc0ext_gpio =3D "/pinctrl/sdmmc0ext/sdmmc0ext-gpio"; sdmmc0ext_bus4 =3D "/pinctrl/sdmmc0ext/sdmmc0ext-bus4"; sdmmc0ext_bus1 =3D "/pinctrl/sdmmc0ext/sdmmc0ext-bus1"; sdmmc0ext_dectn =3D = "/pinctrl/sdmmc0ext/sdmmc0ext-dectn"; sdmmc0ext_wrprt =3D = "/pinctrl/sdmmc0ext/sdmmc0ext-wrprt"; sdmmc0ext_cmd =3D "/pinctrl/sdmmc0ext/sdmmc0ext-cmd"; sdmmc0ext_clk =3D "/pinctrl/sdmmc0ext/sdmmc0ext-clk"; sdmmc0_gpio =3D "/pinctrl/sdmmc0/sdmmc0-gpio"; sdmmc0_bus4 =3D "/pinctrl/sdmmc0/sdmmc0-bus4"; sdmmc0_bus1 =3D "/pinctrl/sdmmc0/sdmmc0-bus1"; sdmmc0_wrprt =3D "/pinctrl/sdmmc0/sdmmc0-wrprt"; sdmmc0_dectn =3D "/pinctrl/sdmmc0/sdmmc0-dectn"; sdmmc0_cmd =3D "/pinctrl/sdmmc0/sdmmc0-cmd"; sdmmc0_clk =3D "/pinctrl/sdmmc0/sdmmc0-clk"; sdmmc0m1_gpio =3D "/pinctrl/sdmmc0-1/sdmmc0m1-gpio"; sdmmc0m1_pwren =3D "/pinctrl/sdmmc0-1/sdmmc0m1-pwren"; sdmmc0m0_gpio =3D "/pinctrl/sdmmc0-0/sdmmc0m0-gpio"; sdmmc0m0_pwren =3D "/pinctrl/sdmmc0-0/sdmmc0m0-pwren"; spdifm2_tx =3D "/pinctrl/spdif-2/spdifm2-tx"; spdifm1_tx =3D "/pinctrl/spdif-1/spdifm1-tx"; spdifm0_tx =3D "/pinctrl/spdif-0/spdifm0-tx"; i2s2m1_sleep =3D "/pinctrl/i2s2-1/i2s2m1-sleep"; i2s2m1_sdo =3D "/pinctrl/i2s2-1/i2s2m1-sdo"; i2s2m1_sdi =3D "/pinctrl/i2s2-1/i2s2m1-sdi"; i2s2m1_lrcktx =3D "/pinctrl/i2s2-1/i2s2m1-lrcktx"; i2s2m1_lrckrx =3D "/pinctrl/i2s2-1/i2sm1-lrckrx"; i2s2m1_sclk =3D "/pinctrl/i2s2-1/i2s2m1-sclk"; i2s2m1_mclk =3D "/pinctrl/i2s2-1/i2s2m1-mclk"; i2s2m0_sleep =3D "/pinctrl/i2s2-0/i2s2m0-sleep"; i2s2m0_sdo =3D "/pinctrl/i2s2-0/i2s2m0-sdo"; i2s2m0_sdi =3D "/pinctrl/i2s2-0/i2s2m0-sdi"; i2s2m0_lrcktx =3D "/pinctrl/i2s2-0/i2s2m0-lrcktx"; i2s2m0_lrckrx =3D "/pinctrl/i2s2-0/i2s2m0-lrckrx"; i2s2m0_sclk =3D "/pinctrl/i2s2-0/i2s2m0-sclk"; i2s2m0_mclk =3D "/pinctrl/i2s2-0/i2s2m0-mclk"; i2s1_sleep =3D "/pinctrl/i2s1/i2s1-sleep"; i2s1_sdio3 =3D "/pinctrl/i2s1/i2s1-sdio3"; i2s1_sdio2 =3D "/pinctrl/i2s1/i2s1-sdio2"; i2s1_sdio1 =3D "/pinctrl/i2s1/i2s1-sdio1"; i2s1_sdo =3D "/pinctrl/i2s1/i2s1-sdo"; i2s1_sdi =3D "/pinctrl/i2s1/i2s1-sdi"; i2s1_lrcktx =3D "/pinctrl/i2s1/i2s1-lrcktx"; i2s1_lrckrx =3D "/pinctrl/i2s1/i2s1-lrckrx"; i2s1_sclk =3D "/pinctrl/i2s1/i2s1-sclk"; i2s1_mclk =3D "/pinctrl/i2s1/i2s1-mclk"; spi0m2_rx =3D "/pinctrl/spi0-2/spi0m2-rx"; spi0m2_tx =3D "/pinctrl/spi0-2/spi0m2-tx"; spi0m2_cs0 =3D "/pinctrl/spi0-2/spi0m2-cs0"; spi0m2_clk =3D "/pinctrl/spi0-2/spi0m2-clk"; spi0m1_cs1 =3D "/pinctrl/spi0-1/spi0m1-cs1"; spi0m1_rx =3D "/pinctrl/spi0-1/spi0m1-rx"; spi0m1_tx =3D "/pinctrl/spi0-1/spi0m1-tx"; spi0m1_cs0 =3D "/pinctrl/spi0-1/spi0m1-cs0"; spi0m1_clk =3D "/pinctrl/spi0-1/spi0m1-clk"; spi0m0_cs1 =3D "/pinctrl/spi0-0/spi0m0-cs1"; spi0m0_rx =3D "/pinctrl/spi0-0/spi0m0-rx"; spi0m0_tx =3D "/pinctrl/spi0-0/spi0m0-tx"; spi0m0_cs0 =3D "/pinctrl/spi0-0/spi0m0-cs0"; spi0m0_clk =3D "/pinctrl/spi0-0/spi0m0-clk"; uart2m1_xfer =3D "/pinctrl/uart2-1/uart2m1-xfer"; uart2m0_xfer =3D "/pinctrl/uart2-0/uart2m0-xfer"; uart1_rts_gpio =3D "/pinctrl/uart1/uart1-rts-gpio"; uart1_rts =3D "/pinctrl/uart1/uart1-rts"; uart1_cts =3D "/pinctrl/uart1/uart1-cts"; uart1_xfer =3D "/pinctrl/uart1/uart1-xfer"; uart0_rts_gpio =3D "/pinctrl/uart0/uart0-rts-gpio"; uart0_rts =3D "/pinctrl/uart0/uart0-rts"; uart0_cts =3D "/pinctrl/uart0/uart0-cts"; uart0_xfer =3D "/pinctrl/uart0/uart0-xfer"; otp_out =3D "/pinctrl/tsadc/otp-out"; otp_gpio =3D "/pinctrl/tsadc/otp-gpio"; pdmm0_fsync_sleep =3D = "/pinctrl/pdm-0/pdmm0-fsync-sleep"; pdmm0_sdi3_sleep =3D "/pinctrl/pdm-0/pdmm0-sdi3-sleep"; pdmm0_sdi2_sleep =3D "/pinctrl/pdm-0/pdmm0-sdi2-sleep"; pdmm0_sdi1_sleep =3D "/pinctrl/pdm-0/pdmm0-sdi1-sleep"; pdmm0_sdi0_sleep =3D "/pinctrl/pdm-0/pdmm0-sdi0-sleep"; pdmm0_clk_sleep =3D "/pinctrl/pdm-0/pdmm0-clk-sleep"; pdmm0_sdi3 =3D "/pinctrl/pdm-0/pdmm0-sdi3"; pdmm0_sdi2 =3D "/pinctrl/pdm-0/pdmm0-sdi2"; pdmm0_sdi1 =3D "/pinctrl/pdm-0/pdmm0-sdi1"; pdmm0_sdi0 =3D "/pinctrl/pdm-0/pdmm0-sdi0"; pdmm0_fsync =3D "/pinctrl/pdm-0/pdmm0-fsync"; pdmm0_clk =3D "/pinctrl/pdm-0/pdmm0-clk"; hdmii2c_xfer =3D "/pinctrl/hdmi_i2c/hdmii2c-xfer"; i2c3_gpio =3D "/pinctrl/i2c3/i2c3-gpio"; i2c3_xfer =3D "/pinctrl/i2c3/i2c3-xfer"; i2c2_xfer =3D "/pinctrl/i2c2/i2c2-xfer"; i2c1_xfer =3D "/pinctrl/i2c1/i2c1-xfer"; i2c0_xfer =3D "/pinctrl/i2c0/i2c0-xfer"; pcfg_input =3D "/pinctrl/pcfg-input"; pcfg_input_high =3D "/pinctrl/pcfg-input-high"; pcfg_output_low =3D "/pinctrl/pcfg-output-low"; pcfg_output_high =3D "/pinctrl/pcfg-output-high"; pcfg_pull_up_12ma =3D "/pinctrl/pcfg-pull-up-12ma"; pcfg_pull_none_12ma =3D "/pinctrl/pcfg-pull-none-12ma"; pcfg_pull_up_8ma =3D "/pinctrl/pcfg-pull-up-8ma"; pcfg_pull_none_8ma =3D "/pinctrl/pcfg-pull-none-8ma"; pcfg_pull_down_4ma =3D "/pinctrl/pcfg-pull-down-4ma"; pcfg_pull_none_4ma =3D "/pinctrl/pcfg-pull-none-4ma"; pcfg_pull_up_4ma =3D "/pinctrl/pcfg-pull-up-4ma"; pcfg_pull_up_2ma =3D "/pinctrl/pcfg-pull-up-2ma"; pcfg_pull_none_2ma =3D "/pinctrl/pcfg-pull-none-2ma"; pcfg_pull_none =3D "/pinctrl/pcfg-pull-none"; pcfg_pull_down =3D "/pinctrl/pcfg-pull-down"; pcfg_pull_up =3D "/pinctrl/pcfg-pull-up"; gpio3 =3D "/pinctrl/gpio3@ff240000"; gpio2 =3D "/pinctrl/gpio2@ff230000"; gpio1 =3D "/pinctrl/gpio1@ff220000"; gpio0 =3D "/pinctrl/gpio0@ff210000"; pinctrl =3D "/pinctrl"; gic =3D "/interrupt-controller@ff811000"; usb_host0_ohci =3D "/usb@ff5d0000"; usb_host0_ehci =3D "/usb@ff5c0000"; usb20_otg =3D "/usb@ff580000"; phy =3D "/ethernet@ff550000/mdio/phy@0"; gmac2phy =3D "/ethernet@ff550000"; gmac2io =3D "/ethernet@ff540000"; emmc =3D "/mmc@ff520000"; sdio =3D "/mmc@ff510000"; sdmmc =3D "/mmc@ff500000"; u2phy_host =3D = "/syscon@ff450000/usb2-phy@100/host-port"; u2phy_otg =3D "/syscon@ff450000/usb2-phy@100/otg-port"; u2phy =3D "/syscon@ff450000/usb2-phy@100"; usb2phy_grf =3D "/syscon@ff450000"; cru =3D "/clock-controller@ff440000"; hdmiphy =3D "/phy@ff430000"; codec_p0_0 =3D "/codec@ff410000/port@0/endpoint"; codec =3D "/codec@ff410000"; hdmi_in_vop =3D "/hdmi@ff3c0000/ports/port/endpoint"; hdmi_in =3D "/hdmi@ff3c0000/ports/port"; hdmi =3D "/hdmi@ff3c0000"; vop_mmu =3D "/iommu@ff373f00"; vop_out_hdmi =3D "/vop@ff370000/port/endpoint@0"; vop_out =3D "/vop@ff370000/port"; vop =3D "/vop@ff370000"; rkvdec_mmu =3D "/iommu@ff360480"; vpu_mmu =3D "/iommu@ff350800"; vpu =3D "/video-codec@ff350000"; vepu_mmu =3D "/iommu@ff340800"; h265e_mmu =3D "/iommu@ff330200"; gpu =3D "/gpu@ff300000"; saradc =3D "/adc@ff280000"; efuse_cpu_version =3D "/efuse@ff260000/cpu-version@1a"; logic_leakage =3D "/efuse@ff260000/logic-leakage@19"; cpu_leakage =3D "/efuse@ff260000/cpu-leakage@17"; efuse_id =3D "/efuse@ff260000/id@7"; efuse =3D "/efuse@ff260000"; tsadc =3D "/tsadc@ff250000"; soc_crit =3D = "/thermal-zones/soc-thermal/trips/soc-crit"; target =3D = "/thermal-zones/soc-thermal/trips/trip-point1"; threshold =3D = "/thermal-zones/soc-thermal/trips/trip-point0"; soc_thermal =3D "/thermal-zones/soc-thermal"; pwm3 =3D "/pwm@ff1b0030"; pwm2 =3D "/pwm@ff1b0020"; pwm1 =3D "/pwm@ff1b0010"; pwm0 =3D "/pwm@ff1b0000"; wdt =3D "/watchdog@ff1a0000"; spi0 =3D "/spi@ff190000"; i2c3 =3D "/i2c@ff180000"; i2c2 =3D "/i2c@ff170000"; vdd_10 =3D "/i2c@ff160000/pmic@18/regulators/LDO_REG3"; vcc18_emmc =3D = "/i2c@ff160000/pmic@18/regulators/LDO_REG2"; vcc_18 =3D "/i2c@ff160000/pmic@18/regulators/LDO_REG1"; vcc_io =3D "/i2c@ff160000/pmic@18/regulators/DCDC_REG4"; vcc_ddr =3D = "/i2c@ff160000/pmic@18/regulators/DCDC_REG3"; vdd_arm =3D = "/i2c@ff160000/pmic@18/regulators/DCDC_REG2"; vdd_logic =3D = "/i2c@ff160000/pmic@18/regulators/DCDC_REG1"; rk805 =3D "/i2c@ff160000/pmic@18"; i2c1 =3D "/i2c@ff160000"; i2c0 =3D "/i2c@ff150000"; uart2 =3D "/serial@ff130000"; uart1 =3D "/serial@ff120000"; uart0 =3D "/serial@ff110000"; power =3D "/syscon@ff100000/power-controller"; grf_gpio =3D "/syscon@ff100000/grf-gpio"; io_domains =3D "/syscon@ff100000/io-domains"; grf =3D "/syscon@ff100000"; pdm =3D "/pdm@ff040000"; spdif_p0_0 =3D "/spdif@ff030000/port/endpoint"; spdif_p0 =3D "/spdif@ff030000/port"; spdif =3D "/spdif@ff030000"; i2s2 =3D "/i2s@ff020000"; i2s1_p0_0 =3D "/i2s@ff010000/port/endpoint"; i2s1_p0 =3D "/i2s@ff010000/port"; i2s1 =3D "/i2s@ff010000"; i2s0 =3D "/i2s@ff000000"; xin24m =3D "/xin24m"; hdmi_sound =3D "/hdmi-sound"; display_subsystem =3D "/display-subsystem"; analog_sound =3D "/analog-sound"; dmac =3D "/bus/dmac@ff1f0000"; amba =3D "/bus"; cpu0_opp_table =3D "/opp_table0"; l2 =3D "/cpus/l2-cache0"; CPU_SLEEP =3D "/cpus/idle-states/cpu-sleep"; cpu3 =3D "/cpus/cpu@3"; cpu2 =3D "/cpus/cpu@2"; cpu1 =3D "/cpus/cpu@1"; cpu0 =3D "/cpus/cpu@0"; }; }; =3D>=20 =3D=3D=3D Mark Millard marklmi at yahoo.com ( dsl-only.net went away in early 2018-Mar)
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