From owner-freebsd-current Thu Dec 5 14:08:13 1996 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.4/8.8.4) id OAA09090 for current-outgoing; Thu, 5 Dec 1996 14:08:13 -0800 (PST) Received: from Octopussy.MI.Uni-Koeln.DE (Octopussy.MI.Uni-Koeln.DE [134.95.166.20]) by freefall.freebsd.org (8.8.4/8.8.4) with SMTP id OAA09065; Thu, 5 Dec 1996 14:07:47 -0800 (PST) Received: from x14.mi.uni-koeln.de (annexr3-4.slip.Uni-Koeln.DE) by Octopussy.MI.Uni-Koeln.DE with SMTP id AA22782 (5.67b/IDA-1.5); Thu, 5 Dec 1996 23:07:35 +0100 Received: (from se@localhost) by x14.mi.uni-koeln.de (8.8.4/8.6.9) id XAA00652; Thu, 5 Dec 1996 23:07:34 +0100 (CET) Message-Id: Date: Thu, 5 Dec 1996 23:07:34 +0100 From: se@freebsd.org (Stefan Esser) To: terry@lambert.org (Terry Lambert) Cc: se@freebsd.org (Stefan Esser), Terje.N.Marthinussen@cc.uit.no, Freebsd-current@freebsd.org Subject: Re: pci-pci bridge on HP netserver References: <199612052030.NAA19852@phaeton.artisoft.com> X-Mailer: Mutt 0.52 Mime-Version: 1.0 In-Reply-To: <199612052030.NAA19852@phaeton.artisoft.com>; from Terry Lambert on Dec 5, 1996 13:30:18 -0700 Sender: owner-current@freebsd.org X-Loop: FreeBSD.org Precedence: bulk On Dec 5, terry@lambert.org (Terry Lambert) wrote: > I don't suppose the PCI code could be changed to dynamically allocate > as many busses as are found... ? You most probably won't believe it: It already does :) But there are limits to what a device independent driver can do. PCI defines the register layout of a PCI to PCI bridge, and a generic driver that probes any number of buses behind it is possible. But in the case of a CPU to PCI bridge, no predefined register set exists. For that reason, there is no standard that defines how to find the bus number of a PCI bridge directly connected to a CPU. It can most often be assumed to be bus 0, since this is the only possibility in a single PCI bus system. But in case of two directly connected PCI buses, one will be bus 0, and the other one will get the number one higher than the highest bus connected to bus 0 through PCI bridges. For a number of reasons it didn't seem to be a good idea to scan for a bus 1 higher than the highest found behind the primary CPU to PCI bridge, but I could try whether this can be made to work reliably with current motherboards. (PCI is designed to allow for a deterministic probing of all attached devices. And this capability is lost, if a scan for buses beyond the first attached to the CPU is introduced ...) The current approach is to have a specially adapted CPU to PCI driver for each chip that is known to deal with different directly attached bus numbers. The Orion was the first PCI chip set designed to have more than one PCI bus directly connected, but this technique has been used for Power-Mac PCI motherboards before. Regards, STefan