Date: Mon, 04 Aug 1997 12:55:32 -0500 From: Tony Overfield <tony@dell.com> To: Terry Lambert <terry@lambert.org> Cc: terry@lambert.org, hackers@FreeBSD.ORG Subject: Re: Pentium II? Message-ID: <3.0.2.32.19970804125532.0070d730@bugs.us.dell.com> In-Reply-To: <199708032034.NAA02135@phaeton.artisoft.com> References: <3.0.2.32.19970803041901.006a69e4@bugs.us.dell.com>
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At 01:34 PM 8/3/97 -0700, Terry Lambert wrote:
>> I tried searching -hackers ("Dell AND disabl* AND cach*") and only
>> found one claim (yours, BTW) that this bug exists. Interestingly,
>> the only reply seemed to disagree with your claim. Perhaps you can
>> offer some better search keywords.
>
>Yes, I can. Search for "PCI" instead of "Dell"; this was a property
>of the Saturn I, Neptune I, and Mecury I chipsets, not a property
>of only Dell computers -- any computer using those chips blew the
>cache line invalidation following a DMA from a PCI controller to
>main memory.
Except that there were work-arounds for the problems which we
implemented. It's simply not true that all of those systems
had those problems.
>> Don't forget than Pentium memory is 64 bits wide and 486/50 memory
>> is 32 bits wide. Thus, your fancy 486/50 memory bus cannot help to
>> explain your faster I/O claims, so maybe you've got a "magic I/O bus."
>
>Actually, PCI busses are only 32 bits wide, so the 64 bit processor
>memory path is totally irrelevent for bus master DMA speed. The
>width limitation is at the bus-to-memory interface, not at the
>processor.
No. PCI memory writes are often posted, combined and written into
DRAM 64 bits at a time.
-
Tony
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