From owner-svn-src-vendor@freebsd.org Thu Aug 24 16:35:05 2017 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8AAACDE3826; Thu, 24 Aug 2017 16:35:05 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2349F83037; Thu, 24 Aug 2017 16:35:05 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v7OGZ4PF073864; Thu, 24 Aug 2017 16:35:04 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v7OGZ3b2073851; Thu, 24 Aug 2017 16:35:03 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201708241635.v7OGZ3b2073851@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 24 Aug 2017 16:35:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r322837 - in vendor/llvm/dist: docs include/llvm/CodeGen lib/CodeGen/SelectionDAG lib/ExecutionEngine lib/IR lib/Object lib/Target/ARM lib/Target/X86 lib/ToolDrivers/llvm-dlltool lib/Tr... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/llvm/dist: docs include/llvm/CodeGen lib/CodeGen/SelectionDAG lib/ExecutionEngine lib/IR lib/Object lib/Target/ARM lib/Target/X86 lib/ToolDrivers/llvm-dlltool lib/Transforms/Scalar lib/Trans... X-SVN-Commit-Revision: 322837 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Aug 2017 16:35:05 -0000 Author: dim Date: Thu Aug 24 16:35:02 2017 New Revision: 322837 URL: https://svnweb.freebsd.org/changeset/base/322837 Log: Vendor import of llvm release_50 branch r311606: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311606 Added: vendor/llvm/dist/test/CodeGen/ARM/Windows/vla-cpsr.ll vendor/llvm/dist/test/CodeGen/X86/pr34139.ll vendor/llvm/dist/test/CodeGen/X86/pr34177.ll vendor/llvm/dist/test/CodeGen/X86/pr34271-1.ll vendor/llvm/dist/test/CodeGen/X86/pr34271.ll vendor/llvm/dist/test/DllTool/coff-decorated.def Deleted: vendor/llvm/dist/test/CodeGen/X86/f16c-schedule.ll vendor/llvm/dist/test/CodeGen/X86/lea32-schedule.ll vendor/llvm/dist/test/CodeGen/X86/lea64-schedule.ll vendor/llvm/dist/test/CodeGen/X86/popcnt-schedule.ll Modified: vendor/llvm/dist/docs/ReleaseNotes.rst vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.h vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp vendor/llvm/dist/lib/ExecutionEngine/CMakeLists.txt vendor/llvm/dist/lib/IR/AutoUpgrade.cpp vendor/llvm/dist/lib/Object/COFFModuleDefinition.cpp vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td vendor/llvm/dist/lib/Target/X86/X86SchedSandyBridge.td vendor/llvm/dist/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp vendor/llvm/dist/lib/ToolDrivers/llvm-dlltool/Options.td vendor/llvm/dist/lib/Transforms/Scalar/LowerAtomic.cpp vendor/llvm/dist/lib/Transforms/Scalar/Reassociate.cpp vendor/llvm/dist/lib/Transforms/Utils/CloneFunction.cpp vendor/llvm/dist/test/Bitcode/upgrade-module-flag.ll vendor/llvm/dist/test/CodeGen/ARM/vzip.ll vendor/llvm/dist/test/CodeGen/X86/avx-schedule.ll vendor/llvm/dist/test/CodeGen/X86/avx512-extract-subvector.ll vendor/llvm/dist/test/CodeGen/X86/extractelement-legalization-store-ordering.ll vendor/llvm/dist/test/CodeGen/X86/fp128-i128.ll vendor/llvm/dist/test/CodeGen/X86/gather-addresses.ll vendor/llvm/dist/test/CodeGen/X86/recip-fastmath.ll vendor/llvm/dist/test/CodeGen/X86/recip-fastmath2.ll vendor/llvm/dist/test/CodeGen/X86/sse-schedule.ll vendor/llvm/dist/test/CodeGen/X86/sse2-schedule.ll vendor/llvm/dist/test/CodeGen/X86/sse3-schedule.ll vendor/llvm/dist/test/CodeGen/X86/sse41-schedule.ll vendor/llvm/dist/test/CodeGen/X86/sse42-schedule.ll vendor/llvm/dist/test/CodeGen/X86/ssse3-schedule.ll vendor/llvm/dist/test/Feature/optnone-opt.ll vendor/llvm/dist/test/Linker/module-flags-pic-1-a.ll vendor/llvm/dist/test/Transforms/Inline/recursive.ll vendor/llvm/dist/test/Transforms/LowerAtomic/atomic-swap.ll vendor/llvm/dist/test/Transforms/Reassociate/canonicalize-neg-const.ll Modified: vendor/llvm/dist/docs/ReleaseNotes.rst ============================================================================== --- vendor/llvm/dist/docs/ReleaseNotes.rst Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/docs/ReleaseNotes.rst Thu Aug 24 16:35:02 2017 (r322837) @@ -77,12 +77,34 @@ Changes to the LLVM IR * Added speculatable attribute indicating a function which does has no side-effects which could inhibit hoisting of calls. -Changes to the ARM Backend +Changes to the Arm Targets -------------------------- - During this release ... +During this release the AArch64 target has: +* A much improved Global ISel at O0. +* Support for ARMv8.1 8.2 and 8.3 instructions. +* New scheduler information for ThunderX2. +* Some SVE type changes but not much more than that. +* Made instruction fusion more aggressive, resulting in speedups + for code making use of AArch64 AES instructions. AES fusion has been + enabled for most Cortex-A cores and the AArch64MacroFusion pass was moved + to the generic MacroFusion pass. +* Added preferred function alignments for most Cortex-A cores. +* OpenMP "offload-to-self" base support. +During this release the ARM target has: + +* Improved, but still mostly broken, Global ISel. +* Scheduling models update, new schedule for Cortex-A57. +* Hardware breakpoint support in LLDB. +* New assembler error handling, with spelling corrections and multiple + suggestions on how to fix problems. +* Improved mixed ARM/Thumb code generation. Some cases in which wrong + relocations were emitted have been fixed. +* Added initial support for mixed ARM/Thumb link-time optimization, using the + thumb-mode target feature. + Changes to the MIPS Target -------------------------- @@ -92,7 +114,29 @@ Changes to the MIPS Target Changes to the PowerPC Target ----------------------------- - During this release ... +* Additional support and exploitation of POWER ISA 3.0: vabsdub, vabsduh, + vabsduw, modsw, moduw, modsd, modud, lxv, stxv, vextublx, vextubrx, vextuhlx, + vextuhrx, vextuwlx, vextuwrx, vextsb2w, vextsb2d, vextsh2w, vextsh2d, and + vextsw2d + +* Implemented Optimal Code Sequences from The PowerPC Compiler Writer's Guide. + +* Enable -fomit-frame-pointer by default. + +* Improved handling of bit reverse intrinsic. + +* Improved handling of memcpy and memcmp functions. + +* Improved handling of branches with static branch hints. + +* Improved codegen for atomic load_acquire. + +* Improved block placement during code layout + +* Many improvements to instruction selection and code generation + + + Changes to the X86 Target ------------------------- Modified: vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h Thu Aug 24 16:35:02 2017 (r322837) @@ -85,7 +85,10 @@ namespace ISD { /// If N is a BUILD_VECTOR node whose elements are all the same constant or /// undefined, return true and return the constant value in \p SplatValue. - bool isConstantSplatVector(const SDNode *N, APInt &SplatValue); + /// This sets \p SplatValue to the smallest possible splat unless AllowShrink + /// is set to false. + bool isConstantSplatVector(const SDNode *N, APInt &SplatValue, + bool AllowShrink = true); /// Return true if the specified node is a BUILD_VECTOR where all of the /// elements are ~0 or undef. Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.h ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Aug 24 16:35:02 2017 (r322837) @@ -627,6 +627,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { (priv SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N); SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N); SDValue ScalarizeVecOp_VSELECT(SDNode *N); + SDValue ScalarizeVecOp_VSETCC(SDNode *N); SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo); Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Aug 24 16:35:02 2017 (r322837) @@ -484,6 +484,9 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode * case ISD::VSELECT: Res = ScalarizeVecOp_VSELECT(N); break; + case ISD::SETCC: + Res = ScalarizeVecOp_VSETCC(N); + break; case ISD::STORE: Res = ScalarizeVecOp_STORE(cast(N), OpNo); break; @@ -558,6 +561,36 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNod return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1), N->getOperand(2)); +} + +/// If the operand is a vector that needs to be scalarized then the +/// result must be v1i1, so just convert to a scalar SETCC and wrap +/// with a scalar_to_vector since the res type is legal if we got here +SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) { + assert(N->getValueType(0).isVector() && + N->getOperand(0).getValueType().isVector() && + "Operand types must be vectors"); + assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type"); + + EVT VT = N->getValueType(0); + SDValue LHS = GetScalarizedVector(N->getOperand(0)); + SDValue RHS = GetScalarizedVector(N->getOperand(1)); + + EVT OpVT = N->getOperand(0).getValueType(); + EVT NVT = VT.getVectorElementType(); + SDLoc DL(N); + // Turn it into a scalar SETCC. + SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, + N->getOperand(2)); + + // Vectors may have a different boolean contents to scalars. Promote the + // value appropriately. + ISD::NodeType ExtendCode = + TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT)); + + Res = DAG.getNode(ExtendCode, DL, NVT, Res); + + return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res); } /// If the value to store is a vector that needs to be scalarized, it must be Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Aug 24 16:35:02 2017 (r322837) @@ -116,7 +116,8 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT, // ISD Namespace //===----------------------------------------------------------------------===// -bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { +bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal, + bool AllowShrink) { auto *BV = dyn_cast(N); if (!BV) return false; @@ -124,9 +125,11 @@ bool ISD::isConstantSplatVector(const SDNode *N, APInt APInt SplatUndef; unsigned SplatBitSize; bool HasUndefs; - EVT EltVT = N->getValueType(0).getVectorElementType(); - return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs) && - EltVT.getSizeInBits() >= SplatBitSize; + unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); + unsigned MinSplatBits = AllowShrink ? 0 : EltSize; + return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs, + MinSplatBits) && + EltSize >= SplatBitSize; } // FIXME: AllOnes and AllZeros duplicate a lot of code. Could these be Modified: vendor/llvm/dist/lib/ExecutionEngine/CMakeLists.txt ============================================================================== --- vendor/llvm/dist/lib/ExecutionEngine/CMakeLists.txt Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/ExecutionEngine/CMakeLists.txt Thu Aug 24 16:35:02 2017 (r322837) @@ -14,6 +14,10 @@ add_llvm_library(LLVMExecutionEngine intrinsics_gen ) +if(BUILD_SHARED_LIBS) + target_link_libraries(LLVMExecutionEngine PUBLIC LLVMRuntimeDyld) +endif() + add_subdirectory(Interpreter) add_subdirectory(MCJIT) add_subdirectory(Orc) Modified: vendor/llvm/dist/lib/IR/AutoUpgrade.cpp ============================================================================== --- vendor/llvm/dist/lib/IR/AutoUpgrade.cpp Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/IR/AutoUpgrade.cpp Thu Aug 24 16:35:02 2017 (r322837) @@ -2239,14 +2239,14 @@ bool llvm::UpgradeDebugInfo(Module &M) { } bool llvm::UpgradeModuleFlags(Module &M) { - const NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); + NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); if (!ModFlags) return false; - bool HasObjCFlag = false, HasClassProperties = false; + bool HasObjCFlag = false, HasClassProperties = false, Changed = false; for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { MDNode *Op = ModFlags->getOperand(I); - if (Op->getNumOperands() < 2) + if (Op->getNumOperands() != 3) continue; MDString *ID = dyn_cast_or_null(Op->getOperand(1)); if (!ID) @@ -2255,7 +2255,24 @@ bool llvm::UpgradeModuleFlags(Module &M) { HasObjCFlag = true; if (ID->getString() == "Objective-C Class Properties") HasClassProperties = true; + // Upgrade PIC/PIE Module Flags. The module flag behavior for these two + // field was Error and now they are Max. + if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { + if (auto *Behavior = + mdconst::dyn_extract_or_null(Op->getOperand(0))) { + if (Behavior->getLimitedValue() == Module::Error) { + Type *Int32Ty = Type::getInt32Ty(M.getContext()); + Metadata *Ops[3] = { + ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), + MDString::get(M.getContext(), ID->getString()), + Op->getOperand(2)}; + ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); + Changed = true; + } + } + } } + // "Objective-C Class Properties" is recently added for Objective-C. We // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module // flag of value 0, so we can correclty downgrade this flag when trying to @@ -2264,9 +2281,10 @@ bool llvm::UpgradeModuleFlags(Module &M) { if (HasObjCFlag && !HasClassProperties) { M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", (uint32_t)0); - return true; + Changed = true; } - return false; + + return Changed; } static bool isOldLoopArgument(Metadata *MD) { Modified: vendor/llvm/dist/lib/Object/COFFModuleDefinition.cpp ============================================================================== --- vendor/llvm/dist/lib/Object/COFFModuleDefinition.cpp Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/Object/COFFModuleDefinition.cpp Thu Aug 24 16:35:02 2017 (r322837) @@ -232,7 +232,13 @@ class Parser { (private) for (;;) { read(); if (Tok.K == Identifier && Tok.Value[0] == '@') { - Tok.Value.drop_front().getAsInteger(10, E.Ordinal); + if (Tok.Value.drop_front().getAsInteger(10, E.Ordinal)) { + // Not an ordinal modifier at all, but the next export (fastcall + // decorated) - complete the current one. + unget(); + Info.Exports.push_back(E); + return Error::success(); + } read(); if (Tok.K == KwNoname) { E.Noname = true; Modified: vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 24 16:35:02 2017 (r322837) @@ -5901,7 +5901,10 @@ static bool isVUZPMask(ArrayRef M, EVT VT, unsign return false; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; for (unsigned j = 0; j < NumElts; ++j) { if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult) return false; @@ -5932,7 +5935,10 @@ static bool isVUZP_v_undef_Mask(ArrayRef M, EVT V unsigned Half = NumElts / 2; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; for (unsigned j = 0; j < NumElts; j += Half) { unsigned Idx = WhichResult; for (unsigned k = 0; k < Half; ++k) { @@ -5972,7 +5978,10 @@ static bool isVZIPMask(ArrayRef M, EVT VT, unsign return false; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; unsigned Idx = WhichResult * NumElts / 2; for (unsigned j = 0; j < NumElts; j += 2) { if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) || @@ -6005,7 +6014,10 @@ static bool isVZIP_v_undef_Mask(ArrayRef M, EVT V return false; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; unsigned Idx = WhichResult * NumElts / 2; for (unsigned j = 0; j < NumElts; j += 2) { if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) || @@ -8793,6 +8805,8 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &M .addReg(ARM::R4, RegState::Implicit | RegState::Kill) .addReg(ARM::R4, RegState::Implicit | RegState::Define) .addReg(ARM::R12, + RegState::Implicit | RegState::Define | RegState::Dead) + .addReg(ARM::CPSR, RegState::Implicit | RegState::Define | RegState::Dead); break; case CodeModel::Large: @@ -8808,6 +8822,8 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &M .addReg(ARM::R4, RegState::Implicit | RegState::Kill) .addReg(ARM::R4, RegState::Implicit | RegState::Define) .addReg(ARM::R12, + RegState::Implicit | RegState::Define | RegState::Dead) + .addReg(ARM::CPSR, RegState::Implicit | RegState::Define | RegState::Dead); break; } Modified: vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Thu Aug 24 16:35:02 2017 (r322837) @@ -29540,8 +29540,9 @@ static bool detectZextAbsDiff(const SDValue &Select, S // In SetLT case, The second operand of the comparison can be either 1 or 0. APInt SplatVal; if ((CC == ISD::SETLT) && - !((ISD::isConstantSplatVector(SetCC.getOperand(1).getNode(), SplatVal) && - SplatVal == 1) || + !((ISD::isConstantSplatVector(SetCC.getOperand(1).getNode(), SplatVal, + /*AllowShrink*/false) && + SplatVal.isOneValue()) || (ISD::isBuildVectorAllZeros(SetCC.getOperand(1).getNode())))) return false; @@ -30628,6 +30629,9 @@ static SDValue combineSelect(SDNode *N, SelectionDAG & // Byte blends are only available in AVX2 if (VT == MVT::v32i8 && !Subtarget.hasAVX2()) return SDValue(); + // There are no 512-bit blend instructions that use sign bits. + if (VT.is512BitVector()) + return SDValue(); assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); APInt DemandedMask(APInt::getSignMask(BitWidth)); @@ -32058,7 +32062,8 @@ static SDValue combineAndMaskToShift(SDNode *N, Select return SDValue(); APInt SplatVal; - if (!ISD::isConstantSplatVector(Op1.getNode(), SplatVal) || + if (!ISD::isConstantSplatVector(Op1.getNode(), SplatVal, + /*AllowShrink*/false) || !SplatVal.isMask()) return SDValue(); @@ -32642,7 +32647,8 @@ static SDValue detectUSatPattern(SDValue In, EVT VT) { "Unexpected types for truncate operation"); APInt C; - if (ISD::isConstantSplatVector(In.getOperand(1).getNode(), C)) { + if (ISD::isConstantSplatVector(In.getOperand(1).getNode(), C, + /*AllowShrink*/false)) { // C should be equal to UINT32_MAX / UINT16_MAX / UINT8_MAX according // the element size of the destination type. return C.isMask(VT.getScalarSizeInBits()) ? In.getOperand(0) : @@ -35346,7 +35352,8 @@ static SDValue combineIncDecVector(SDNode *N, Selectio SDNode *N1 = N->getOperand(1).getNode(); APInt SplatVal; - if (!ISD::isConstantSplatVector(N1, SplatVal) || !SplatVal.isOneValue()) + if (!ISD::isConstantSplatVector(N1, SplatVal, /*AllowShrink*/false) || + !SplatVal.isOneValue()) return SDValue(); SDValue AllOnesVec = getOnesVector(VT, DAG, SDLoc(N)); Modified: vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td Thu Aug 24 16:35:02 2017 (r322837) @@ -3619,8 +3619,8 @@ let Predicates = [HasVLX] in { def : Pat<(alignedstore256 (v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))), addr:$dst), (VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>; - def : Pat<(alignedstore (v8f32 (extract_subvector - (v16f32 VR512:$src), (iPTR 0))), addr:$dst), + def : Pat<(alignedstore256 (v8f32 (extract_subvector + (v16f32 VR512:$src), (iPTR 0))), addr:$dst), (VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>; def : Pat<(alignedstore256 (v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))), addr:$dst), Modified: vendor/llvm/dist/lib/Target/X86/X86SchedSandyBridge.td ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86SchedSandyBridge.td Thu Aug 24 15:12:16 2017 (r322836) +++ vendor/llvm/dist/lib/Target/X86/X86SchedSandyBridge.td Thu Aug 24 16:35:02 2017 (r322837) @@ -24,8 +24,8 @@ def SandyBridgeModel : SchedMachineModel { // Based on the LSD (loop-stream detector) queue size. let LoopMicroOpBufferSize = 28; - // This flag is set to allow the scheduler to assign - // a default model to unrecognized opcodes. + // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. let CompleteModel = 0; } @@ -48,7 +48,6 @@ def SBPort23 : ProcResource<2>; def SBPort4 : ProcResource<1>; // Many micro-ops are capable of issuing on multiple ports. -def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; @@ -116,10 +115,10 @@ def : WriteRes; defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; // 10-14 cycles. defm : SBWriteResPair; defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; @@ -135,11 +134,11 @@ def : WriteRes; -defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; defm : SBWriteResPair; def : WriteRes { let Latency = 2; @@ -149,15 +148,13 @@ def : WriteRes { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; +def : WriteRes { + let Latency = 6; + let ResourceCycles = [1, 1, 1]; } -def : WriteRes { - let Latency = 11; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; +def : WriteRes { + let Latency = 6; + let ResourceCycles = [1, 1, 1, 1]; } //////////////////////////////////////////////////////////////////////////////// @@ -207,15 +204,13 @@ def : WriteRes { - let Latency = 11; - let NumMicroOps = 3; +def : WriteRes { + let Latency = 3; let ResourceCycles = [3]; } -def : WriteRes { - let Latency = 17; - let NumMicroOps = 4; - let ResourceCycles = [3,1]; +def : WriteRes { + let Latency = 3; + let ResourceCycles = [3, 1]; } // Packed Compare Explicit Length Strings, Return Index @@ -229,26 +224,22 @@ def : WriteRes { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; +def : WriteRes { + let Latency = 8; + let ResourceCycles = [2]; } -def : WriteRes { - let Latency = 13; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; +def : WriteRes { + let Latency = 8; + let ResourceCycles = [2, 1]; } -def : WriteRes { - let Latency = 12; - let NumMicroOps = 2; +def : WriteRes { + let Latency = 8; let ResourceCycles = [2]; } -def : WriteRes { - let Latency = 18; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; +def : WriteRes { + let Latency = 8; + let ResourceCycles = [2, 1]; } def : WriteRes { @@ -281,2407 +272,4 @@ def : WriteRes; defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; - -// Remaining SNB instrs. - -def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSLLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSLLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSLLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRADri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRAWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VCVTSS2SDrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSLLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSLLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSLLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRADri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRAWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDYrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSYrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSrr")>; - -def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup1], (instregex "COMP_FST0r")>; -def: InstRW<[SBWriteResGroup1], (instregex "COM_FST0r")>; -def: InstRW<[SBWriteResGroup1], (instregex "UCOM_FPr")>; -def: InstRW<[SBWriteResGroup1], (instregex "UCOM_Fr")>; - -def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ANDNPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ANDPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ANDPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP")>; -def: InstRW<[SBWriteResGroup2], (instregex "FFREE")>; -def: InstRW<[SBWriteResGroup2], (instregex "FINCSTP")>; -def: InstRW<[SBWriteResGroup2], (instregex "FNOP")>; -def: InstRW<[SBWriteResGroup2], (instregex "INSERTPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "JMP64r")>; -def: InstRW<[SBWriteResGroup2], (instregex "LD_Frr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOV64toPQIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVAPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVAPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVDDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVDI2PDIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVHLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVLHPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSHDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSLDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVUPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVUPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ORPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "RETQ")>; -def: InstRW<[SBWriteResGroup2], (instregex "SHUFPDrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "SHUFPSrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "ST_FPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ST_Frr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VEXTRACTF128rr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VINSERTF128rr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VINSERTPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrm")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrm")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDYrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSYrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VXORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VXORPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "XORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "XORPSrr")>; - -def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup3], (instregex "LEA64_32r")>; - -def SBWriteResGroup4 : SchedWriteRes<[SBPort0]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup4], (instregex "BLENDPDrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "BLENDPSrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "BT32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BT32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTC32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTC32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTR32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTR32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTS32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTS32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "CDQ")>; -def: InstRW<[SBWriteResGroup4], (instregex "CQO")>; -def: InstRW<[SBWriteResGroup4], (instregex "LAHF")>; -def: InstRW<[SBWriteResGroup4], (instregex "SAHF")>; -def: InstRW<[SBWriteResGroup4], (instregex "SAR32ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SAR8ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETAEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETBr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETGEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETGr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETLEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETLr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNOr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNPr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNSr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETOr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETPr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETSr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL32ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL64r1")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL8r1")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL8ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHR32ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHR8ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDYrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSYrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQAYrr")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQArr")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUYrr")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUrr")>; - -def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup5], (instregex "KORTESTBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PADDQirr")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNR64irr")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "PABSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PABSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PABSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKSSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKSSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKUSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKUSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PALIGNRrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PAVGBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PAVGWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PBLENDWrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFDri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFHWri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFLWri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSLLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSRLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHQDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLQDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VMASKMOVPSYrm")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPABSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPABSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPABSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPALIGNRrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPAVGBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPAVGWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPBLENDWrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFDri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFLWri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSLLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSRLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLQDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLWDrr")>; - -def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup6], (instregex "ADD32ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "ADD32rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND32ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "CBW")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMC")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP16ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP32i32")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "CWDE")>; -def: InstRW<[SBWriteResGroup6], (instregex "DEC64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "DEC8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "INC64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "INC8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOV32rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOV8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr16")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr8")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr16")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr8")>; -def: InstRW<[SBWriteResGroup6], (instregex "NEG64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "NOT64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "STC")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR32rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR8rr")>; - -def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> { - let Latency = 2; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPDrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPSrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "MOVPDI2DIrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "MOVPQIto64rr")>; -def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDYrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPSrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVPDI2DIrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVPQIto64rr")>; - -def SBWriteResGroup9 : SchedWriteRes<[SBPort0]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0")>; -def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPSrr0")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROL32ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROL8ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROR32ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROR8ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "SETAr")>; -def: InstRW<[SBWriteResGroup9], (instregex "SETBEr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDYrr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDrr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSYrr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSrr")>; - -def SBWriteResGroup10 : SchedWriteRes<[SBPort15]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup10], (instregex "VPBLENDVBrr")>; - -def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup11], (instregex "SCASB")>; -def: InstRW<[SBWriteResGroup11], (instregex "SCASL")>; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***