Date: Mon, 6 Oct 2014 11:51:32 -0300 From: Martin Galvan <omgalvan.86@gmail.com> To: Ian Lepore <ian@freebsd.org> Cc: freebsd-drivers@freebsd.org, freebsd-embedded@freebsd.org Subject: Re: A few questions about SD/MMC drivers Message-ID: <CAN19L9FivCE1OHH-mv5H%2BvOBYHGu-ErGaMvQsvxX=fSFicMrvg@mail.gmail.com> In-Reply-To: <1412606675.12052.112.camel@revolution.hippie.lan> References: <CAN19L9ENsuAR6_aXwJSRdfDz6UgE6kU%2BrCkGGsdK7tRcUes%2B0w@mail.gmail.com> <FEB6A362-40F7-4418-8B28-F03506F6C365@bsdimp.com> <CAN19L9FudV6PtsmE359Wfb216am3eaiEJtd6ixq2eOfJDZHbkA@mail.gmail.com> <1412606675.12052.112.camel@revolution.hippie.lan>
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2014-10-06 11:44 GMT-03:00 Ian Lepore <ian@freebsd.org>: > On Sun, 2014-10-05 at 21:32 -0300, Martin Galvan wrote: >> Hi Warner! Thanks for your answer. >> >> 2014-10-05 20:06 GMT-03:00 Warner Losh <imp@bsdimp.com>: >> > On Oct 5, 2014, at 4:05 PM, Martin Galvan <omgalvan.86@gmail.com> wrot= e: >> > >> >> 2) The code I'm working on is based off the Linux driver for the same >> >> host, which as of today stands as the only "documentation", so to >> >> speak, on that particular host. According to the Linux driver, we nee= d >> >> to do a phase shift adjustment while setting the clock in the set_ios >> >> function. That involves several steps, one of which is calling >> >> clk_set_rate, which seems to be a function many other Linux drivers >> >> use. As I'm not familiar with Linux kernel internals, so far I haven'= t >> >> been able to find the equivalent for that function on BSD, so how >> >> should I go about this? >> > >> > Most likely you=E2=80=99ll need to write the clock infrastructure for = allwinner to >> > make this work. I don=E2=80=99t believe that it is actually there toda= y. Note: I=E2=80=99ve >> > not looked at the allwinner core code in a long time, so maybe this >> > has already been rectified. >> >> Well, there's a a10_clk.c file in the current tree that (sort of) >> takes care of the clocking for Allwinner. >> >> > clk_set_rate in Linux adjusts the produced clock frequency for a clock >> > that=E2=80=99s programmable in the SoC. >> > > The phase shift adjustment thing sounds like support for the Ultra rates > (clocks faster than 50mhz and clocking data on both clock edges). I > think people would be plenty happy to have 25 and 50mhz support without > any of the ultra rates, for starters. That may let you ignore the phase > tuning stuff. Maybe look at the driver in u-boot if it has one, often > the u-boot drivers are simplified compared to the full linux driver. I'm not sure if that's exactly the case. Quoting the author of the Linux dr= iver: "you have to clock up mmc0 mod clock and adapt the phase shift in order to compensate the delays caused by line distance on the PCB. This is done in here: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/drive= rs/mmc/host/sunxi-mmc.c?id=3D3cbcb16095f916f50a5a55066fcc4be06946ce1e#n617 " > Also, it may be that if you do an "mmc init" in u-boot the driver will > work without doing any more clock stuff at all, because u-boot will do > all the hardware setup. It's best if our drivers can set up what they > need for themselves, but letting u-boot do it is a good starting point. That's a great idea, I never thought of looking at the u-boot driver. I'll try out DMA and multiblock first anyways, and if it works fast enough to at least be able to boot directly from the SD card I'll send you guys the patches.
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