From owner-svn-src-all@freebsd.org Sun Nov 29 15:24:02 2020 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 1C7A24A4ECD; Sun, 29 Nov 2020 15:24:02 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4CkXFt0H0Pz4lb5; Sun, 29 Nov 2020 15:24:02 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id F06EA13B39; Sun, 29 Nov 2020 15:24:01 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 0ATFO1Ut022771; Sun, 29 Nov 2020 15:24:01 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 0ATFO12F022763; Sun, 29 Nov 2020 15:24:01 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <202011291524.0ATFO12F022763@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Sun, 29 Nov 2020 15:24:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r368154 - in head/sys: arm/arm arm/include arm/mv conf X-SVN-Group: head X-SVN-Commit-Author: mmel X-SVN-Commit-Paths: in head/sys: arm/arm arm/include arm/mv conf X-SVN-Commit-Revision: 368154 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Nov 2020 15:24:02 -0000 Author: mmel Date: Sun Nov 29 15:24:00 2020 New Revision: 368154 URL: https://svnweb.freebsd.org/changeset/base/368154 Log: Remove remaining fragments of code for older already ceased ARM versions. Deleted: head/sys/arm/arm/cpufunc_asm_arm9.S head/sys/arm/arm/cpufunc_asm_armv4.S head/sys/arm/arm/cpufunc_asm_armv5_ec.S head/sys/arm/arm/cpufunc_asm_sheeva.S head/sys/arm/mv/std.mv Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/include/cpufunc.h head/sys/arm/include/md_var.h head/sys/conf/files.arm Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Sun Nov 29 15:04:39 2020 (r368153) +++ head/sys/arm/arm/cpufunc.c Sun Nov 29 15:24:00 2020 (r368154) @@ -80,9 +80,6 @@ u_int arm_cache_level; u_int arm_cache_type[14]; u_int arm_cache_loc; -#if defined(CPU_ARM9E) -static void arm10_setup(void); -#endif #ifdef CPU_MV_PJ4B static void pj4bv7_setup(void); #endif @@ -93,107 +90,6 @@ static void arm11x6_setup(void); static void cortexa_setup(void); #endif -#if defined(CPU_ARM9E) -struct cpu_functions armv5_ec_cpufuncs = { - /* CPU functions */ - - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - armv5_ec_setttb, /* Setttb */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - arm9_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - armv5_ec_icache_sync_range, /* icache_sync_range */ - - armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ - armv5_ec_dcache_wbinv_range, /* dcache_wbinv_range */ - armv5_ec_dcache_inv_range, /* dcache_inv_range */ - armv5_ec_dcache_wb_range, /* dcache_wb_range */ - - armv4_idcache_inv_all, /* idcache_inv_all */ - armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ - armv5_ec_idcache_wbinv_range, /* idcache_wbinv_range */ - - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ - - /* Other functions */ - - armv4_drain_writebuf, /* drain_writebuf */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - arm9_context_switch, /* context_switch */ - - arm10_setup /* cpu setup */ - -}; - -struct cpu_functions sheeva_cpufuncs = { - /* CPU functions */ - - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - sheeva_setttb, /* Setttb */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - arm9_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - armv5_ec_icache_sync_range, /* icache_sync_range */ - - armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ - sheeva_dcache_wbinv_range, /* dcache_wbinv_range */ - sheeva_dcache_inv_range, /* dcache_inv_range */ - sheeva_dcache_wb_range, /* dcache_wb_range */ - - armv4_idcache_inv_all, /* idcache_inv_all */ - armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ - sheeva_idcache_wbinv_range, /* idcache_wbinv_all */ - - sheeva_l2cache_wbinv_all, /* l2cache_wbinv_all */ - sheeva_l2cache_wbinv_range, /* l2cache_wbinv_range */ - sheeva_l2cache_inv_range, /* l2cache_inv_range */ - sheeva_l2cache_wb_range, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ - - /* Other functions */ - - armv4_drain_writebuf, /* drain_writebuf */ - - sheeva_cpu_sleep, /* sleep */ - - /* Soft functions */ - - arm9_context_switch, /* context_switch */ - - arm10_setup /* cpu setup */ -}; -#endif /* CPU_ARM9E */ - #ifdef CPU_MV_PJ4B struct cpu_functions pj4bv7_cpufuncs = { /* Cache operations */ @@ -257,11 +153,6 @@ struct cpu_functions cortexa_cpufuncs = { struct cpu_functions cpufuncs; u_int cputype; -#if defined (CPU_ARM9E) || \ - defined(CPU_ARM1176) || \ - defined(CPU_MV_PJ4B) || \ - defined(CPU_CORTEXA) || defined(CPU_KRAIT) - static void get_cachetype_cp15(void); /* Additional cache information local to this file. Log2 of some of the @@ -371,7 +262,6 @@ get_cachetype_cp15(void) arm_dcache_align_mask = arm_dcache_align - 1; } } -#endif /* ARM9 || XSCALE */ /* * Cannot panic here as we may not have a console yet ... @@ -383,38 +273,6 @@ set_cpufuncs(void) cputype = cp15_midr_get(); cputype &= CPU_ID_CPU_MASK; -#if defined(CPU_ARM9E) - if (cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD || - cputype == CPU_ID_MV88FR571_41) { - uint32_t sheeva_ctrl; - - sheeva_ctrl = (MV_DC_STREAM_ENABLE | MV_BTB_DISABLE | - MV_L2_ENABLE); - /* - * Workaround for Marvell MV78100 CPU: Cache prefetch - * mechanism may affect the cache coherency validity, - * so it needs to be disabled. - * - * Refer to errata document MV-S501058-00C.pdf (p. 3.1 - * L2 Prefetching Mechanism) for details. - */ - if (cputype == CPU_ID_MV88FR571_VD || - cputype == CPU_ID_MV88FR571_41) - sheeva_ctrl |= MV_L2_PREFETCH_DISABLE; - - sheeva_control_ext(0xffffffff & ~MV_WA_ENABLE, sheeva_ctrl); - - cpufuncs = sheeva_cpufuncs; - get_cachetype_cp15(); - pmap_pte_init_generic(); - goto out; - } else if (cputype == CPU_ID_ARM926EJS) { - cpufuncs = armv5_ec_cpufuncs; - get_cachetype_cp15(); - pmap_pte_init_generic(); - goto out; - } -#endif /* CPU_ARM9E */ #if defined(CPU_ARM1176) if (cputype == CPU_ID_ARM1176JZS) { cpufuncs = arm1176_cpufuncs; @@ -466,43 +324,6 @@ out: * CPU Setup code */ -#if defined(CPU_ARM9E) -static void -arm10_setup(void) -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_BPRD_ENABLE - | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Now really make sure they are clean. */ - __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); - - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - - /* Set the control register */ - cpu_control(0xffffffff, cpuctrl); - - /* And again. */ - cpu_idcache_wbinv_all(); -} -#endif /* CPU_ARM9E || CPU_ARM10 */ #if defined(CPU_ARM1176) \ || defined(CPU_MV_PJ4B) \ Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Sun Nov 29 15:04:39 2020 (r368153) +++ head/sys/arm/include/cpufunc.h Sun Nov 29 15:24:00 2020 (r368154) @@ -93,24 +93,7 @@ void cpufunc_nullop (void); u_int cpufunc_control (u_int clear, u_int bic); void cpu_domains (u_int domains); -#if defined(CPU_ARM9E) -void arm9_tlb_flushID_SE (u_int va); -void arm9_context_switch (void); -u_int sheeva_control_ext (u_int, u_int); -void sheeva_cpu_sleep (int); -void sheeva_setttb (u_int); -void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); -void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); -void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); -void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); - -void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); -void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); -void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); -void sheeva_l2cache_wbinv_all (void); -#endif - #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) void armv7_cpu_sleep (int); #endif @@ -122,26 +105,6 @@ void pj4b_config (void); void arm11x6_sleep (int); /* no ref. for errata */ #endif -#if defined(CPU_ARM9E) -void armv5_ec_setttb(u_int); - -void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); - -void armv5_ec_dcache_wbinv_all(void); -void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); -void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); -void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); - -void armv5_ec_idcache_wbinv_all(void); -void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); - -void armv4_tlb_flushID (void); -void armv4_tlb_flushD (void); -void armv4_tlb_flushD_SE (u_int va); - -void armv4_drain_writebuf (void); -void armv4_idcache_inv_all (void); -#endif /* * Macros for manipulating CPU interrupts Modified: head/sys/arm/include/md_var.h ============================================================================== --- head/sys/arm/include/md_var.h Sun Nov 29 15:04:39 2020 (r368153) +++ head/sys/arm/include/md_var.h Sun Nov 29 15:24:00 2020 (r368154) @@ -54,14 +54,8 @@ extern int _min_bzero_size; enum cpu_class { CPU_CLASS_NONE, - CPU_CLASS_ARM9TDMI, - CPU_CLASS_ARM9ES, - CPU_CLASS_ARM9EJS, - CPU_CLASS_ARM10E, - CPU_CLASS_ARM10EJ, CPU_CLASS_CORTEXA, CPU_CLASS_KRAIT, - CPU_CLASS_XSCALE, CPU_CLASS_ARM11J, CPU_CLASS_MARVELL }; Modified: head/sys/conf/files.arm ============================================================================== --- head/sys/conf/files.arm Sun Nov 29 15:04:39 2020 (r368153) +++ head/sys/conf/files.arm Sun Nov 29 15:24:00 2020 (r368154) @@ -11,13 +11,9 @@ arm/arm/busdma_machdep.c standard arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard -arm/arm/cpufunc_asm_arm9.S optional cpu_arm9e arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 -arm/arm/cpufunc_asm_armv4.S optional cpu_arm9e -arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b -arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S standard arm/arm/db_disasm.c optional ddb