From owner-svn-src-head@FreeBSD.ORG Mon Oct 6 10:58:54 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id DB703D91; Mon, 6 Oct 2014 10:58:54 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C874484C; Mon, 6 Oct 2014 10:58:54 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s96Awsut007883; Mon, 6 Oct 2014 10:58:54 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s96Awstt007882; Mon, 6 Oct 2014 10:58:54 GMT (envelope-from mav@FreeBSD.org) Message-Id: <201410061058.s96Awstt007882@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Mon, 6 Oct 2014 10:58:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r272606 - head/sys/dev/ahci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Oct 2014 10:58:55 -0000 Author: mav Date: Mon Oct 6 10:58:54 2014 New Revision: 272606 URL: https://svnweb.freebsd.org/changeset/base/272606 Log: Use r271207 optimization only for MSI-enabled HBAs. It was found that VirtualBox' AHCI does not allow nterrupt to be cleared before the interrupt status register is read, causing interrupt storm. AHCI specification allows to skip this register use when multi-vector MSI is enabled and so interrupting port is known. For single-vector MSI that is not stated explicitly, but if the port is only one, it is obviously known too. Modified: head/sys/dev/ahci/ahci.c Modified: head/sys/dev/ahci/ahci.c ============================================================================== --- head/sys/dev/ahci/ahci.c Mon Oct 6 09:52:28 2014 (r272605) +++ head/sys/dev/ahci/ahci.c Mon Oct 6 10:58:54 2014 (r272606) @@ -360,7 +360,7 @@ ahci_setup_interrupt(device_t dev) for (i = 0; i < ctlr->numirqs; i++) { ctlr->irqs[i].ctlr = ctlr; ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); - if (ctlr->channels == 1 && !ctlr->ccc) + if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; else if (ctlr->numirqs == 1 || i >= ctlr->channels || (ctlr->ccc && i == ctlr->cccv))