Date: Sat, 30 Aug 1997 18:29:51 +0200 (MET DST) From: Luigi Rizzo <luigi@labinfo.iet.unipi.it> To: dec@phoenix.its.rpi.edu (David E. Cross) Cc: hackers@FreeBSD.ORG, multimedia@FreeBSD.ORG Subject: IRQ problem (was Re: IRQ timing) Message-ID: <199708301629.SAA03050@labinfo.iet.unipi.it> In-Reply-To: <Pine.BSF.3.96.970830112012.15813A-100000@phoenix.its.rpi.edu> from "David E. Cross" at Aug 30, 97 11:22:25 am
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> I just sent a message to the OSS people, and they mentioned that some of
> the problem I am experiencing is a result of some tight IRQ timing that
> the FreeBSD kernel has (ie, it takes too long to transfer the data). I
would you care to mention what problem are you experiencing ?
Curiously I have a related question, so hope people would excluse the
crosspost..
I have a problem of missing interrupts with a device, but am not
sure if it is a broken device, an intrinsic problem with ISA
interrupts, a problem with my 82371 chipset, or what. So some help
would be appreciated.
Briefly, the question is: is there any feedback on the ISA bus to
signal a device WITH MULTIPLE INTERNAL SOURCES that an interrupt
has been served by the CPU and it can lower the interrupt line ?
The device I have problems with is the OPTI931, a full duplex audio
chip. It has multiple internal interrupt sources, all routed to a
single ISA interrupt line. It is possible to acknowledge separately
each interrupt source. My interrupt driver loops on the interrupt
status register and returns when there are no more active sources,
acking the various sources as they are served.
Since the cause for interrupts is the completion of a dma transfer,
I have an alternate way to check that the conditions for an interrupt
have occurred. Very frequently, when both DMA channels are active,
I find that the DMA transfer is complete, yet I don't get the
interrupt I expect (luckily in most cases I can recover because at
the same time I get an interrupt on the other channel, can test
the ISA DMA count, and do the appropriate actions).
At first I thought it was a problem with the board, but am not that
sure now.
Apparently the only feedback I can give to the device is through
the individual interrupt acknowledge bits in the device. But when
multiple internal sources are active, and one of them is not acked
by the interrupt service routine (e.g. because it goes high after
I read the status register) then the IRQ line should stay high. If
ISA interrupts are really edge triggered, any interrupt not served
when it occurs would be irremediably lost, or what ?
Evidently things must be different from what I think because other
similar devices (e.g. the CS4236) seem to work fine, but where is the
trick ?
Thanks
Luigi
-----------------------------+--------------------------------------
Luigi Rizzo | Dip. di Ingegneria dell'Informazione
email: luigi@iet.unipi.it | Universita' di Pisa
tel: +39-50-568533 | via Diotisalvi 2, 56126 PISA (Italy)
fax: +39-50-568522 | http://www.iet.unipi.it/~luigi/
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