Date: Mon, 4 Jun 2012 15:50:50 +0300 From: Konstantin Belousov <kostikbel@gmail.com> To: Tijl Coosemans <tijl@freebsd.org> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r236456 - in head/sys: amd64/include i386/include Message-ID: <20120604125050.GA85127@deviant.kiev.zoral.com.ua> In-Reply-To: <4FCC873B.90104@freebsd.org> References: <201206021810.q52IAGZA004238@svn.freebsd.org> <4FCC873B.90104@freebsd.org>
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--5vNYLRcllDrimb99 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 04, 2012 at 12:00:27PM +0200, Tijl Coosemans wrote: > On 02-06-2012 20:10, Konstantin Belousov wrote: > > Author: kib > > Date: Sat Jun 2 18:10:16 2012 > > New Revision: 236456 > > URL: http://svn.freebsd.org/changeset/base/236456 > >=20 > > Log: > > Use plain store for atomic_store_rel on x86, instead of implicitly > > locked xchg instruction. IA32 memory model guarantees that store has > > release semantic, since stores cannot pass loads or stores. >=20 > They can pass non-temporal stores can't they? Sure. But (our) barriers only work for WB memory accesses, in respect to ot= her WB memory accesses. The atomic(9) contains not quite explicit mention of the requirement, for ia32 and more direct notion for ia64. It could probably be reworded to mention memory access type explicitely for ia32 too. At least the code which I saw and maintain which uses the mixed accesses to the same physical page, sometime including non-CPU caches coherency protocols, use explicit {s,m}fence barriers as needed. --5vNYLRcllDrimb99 Content-Type: application/pgp-signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (FreeBSD) iEYEARECAAYFAk/MrykACgkQC3+MBN1Mb4gfcwCfZegTw+qe1tj4qPpT8osb1267 SpgAnivKjpW3WAIf7FOx7DrJtkAcloaL =QyCF -----END PGP SIGNATURE----- --5vNYLRcllDrimb99--
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