From owner-svn-src-all@freebsd.org Mon Dec 21 01:48:17 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5D979A4D5C8; Mon, 21 Dec 2015 01:48:17 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2ADB71606; Mon, 21 Dec 2015 01:48:17 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tBL1mGiN055215; Mon, 21 Dec 2015 01:48:16 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tBL1mG8e055214; Mon, 21 Dec 2015 01:48:16 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201512210148.tBL1mG8e055214@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Mon, 21 Dec 2015 01:48:16 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r292526 - head/sys/mips/mips X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Dec 2015 01:48:17 -0000 Author: adrian Date: Mon Dec 21 01:48:16 2015 New Revision: 292526 URL: https://svnweb.freebsd.org/changeset/base/292526 Log: [mips] print out l2 cache configuration if it exists. The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board has an L2 cache: Cache info: picache_stride = 4096 picache_loopcount = 8 pdcache_stride = 4096 pdcache_loopcount = 8 cpu0: Ingenic Xburst processor v79.2 MMU: Standard TLB, 32 entries L1 i-cache: 8 ways of 128 sets, 32 bytes per line L1 d-cache: 8 ways of 128 sets, 32 bytes per line L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size Config1=0xbe67338b Config2=0x80000267 Config3=0x20 Modified: head/sys/mips/mips/cpu.c Modified: head/sys/mips/mips/cpu.c ============================================================================== --- head/sys/mips/mips/cpu.c Mon Dec 21 01:14:54 2015 (r292525) +++ head/sys/mips/mips/cpu.c Mon Dec 21 01:48:16 2015 (r292526) @@ -318,6 +318,18 @@ cpu_identify(void) cpuinfo.l1.dc_nsets, cpuinfo.l1.dc_linesize); } + printf(" L2 cache: "); + if (cpuinfo.l2.dc_linesize == 0) { + printf("disabled"); + } else { + printf("%d ways of %d sets, %d bytes per line, " + "%d KiB total size\n", + cpuinfo.l2.dc_nways, + cpuinfo.l2.dc_nsets, + cpuinfo.l2.dc_linesize, + cpuinfo.l2.dc_size / 1024); + } + cfg0 = mips_rd_config(); /* If config register selection 1 does not exist, exit. */ if (!(cfg0 & MIPS_CONFIG_CM)) @@ -335,6 +347,7 @@ cpu_identify(void) * Config2 contains no useful information other then Config3 * existence flag */ + printf(" Config2=0x%08x\n", cfg2); /* If config register selection 3 does not exist, exit. */ if (!(cfg2 & MIPS_CONFIG_CM))