Date: Wed, 13 Jan 2016 04:11:04 +0000 (UTC) From: Glen Barber <gjb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r293803 - in projects/release-pkg: . etc lib/libc/sys share/examples/ypldap share/man/man4 sys/arm/arm sys/boot/efi/libefi sys/boot/uboot/lib sys/dev/sfxge/common sys/dev/uart usr.sbin/... Message-ID: <201601130411.u0D4B441097625@repo.freebsd.org>
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Author: gjb Date: Wed Jan 13 04:11:04 2016 New Revision: 293803 URL: https://svnweb.freebsd.org/changeset/base/293803 Log: MFH Sponsored by: The FreeBSD Foundation Added: projects/release-pkg/share/examples/ypldap/ - copied from r293802, head/share/examples/ypldap/ projects/release-pkg/sys/dev/uart/uart_ppstypes.h - copied unchanged from r293802, head/sys/dev/uart/uart_ppstypes.h Modified: projects/release-pkg/UPDATING projects/release-pkg/etc/master.passwd projects/release-pkg/lib/libc/sys/futimens.c projects/release-pkg/lib/libc/sys/utimensat.2 projects/release-pkg/lib/libc/sys/utimensat.c projects/release-pkg/share/man/man4/uart.4 projects/release-pkg/sys/arm/arm/pmap-v6-new.c projects/release-pkg/sys/boot/efi/libefi/libefi.c projects/release-pkg/sys/boot/uboot/lib/copy.c projects/release-pkg/sys/dev/sfxge/common/efx.h projects/release-pkg/sys/dev/sfxge/common/efx_check.h projects/release-pkg/sys/dev/sfxge/common/efx_filter.c projects/release-pkg/sys/dev/sfxge/common/efx_impl.h projects/release-pkg/sys/dev/sfxge/common/efx_intr.c projects/release-pkg/sys/dev/sfxge/common/efx_mac.c projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.c projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.h projects/release-pkg/sys/dev/sfxge/common/efx_regs_mcdi.h projects/release-pkg/sys/dev/sfxge/common/efx_rx.c projects/release-pkg/sys/dev/sfxge/common/hunt_ev.c projects/release-pkg/sys/dev/sfxge/common/hunt_filter.c projects/release-pkg/sys/dev/sfxge/common/hunt_impl.h projects/release-pkg/sys/dev/sfxge/common/hunt_intr.c projects/release-pkg/sys/dev/sfxge/common/hunt_mac.c projects/release-pkg/sys/dev/sfxge/common/hunt_mcdi.c projects/release-pkg/sys/dev/sfxge/common/hunt_nvram.c projects/release-pkg/sys/dev/sfxge/common/hunt_rx.c projects/release-pkg/sys/dev/sfxge/common/mcdi_mon.c projects/release-pkg/sys/dev/sfxge/common/siena_flash.h projects/release-pkg/sys/dev/sfxge/common/siena_impl.h projects/release-pkg/sys/dev/sfxge/common/siena_mcdi.c projects/release-pkg/sys/dev/sfxge/common/siena_nvram.c projects/release-pkg/sys/dev/sfxge/common/siena_vpd.c projects/release-pkg/sys/dev/uart/uart_bus.h projects/release-pkg/sys/dev/uart/uart_core.c projects/release-pkg/sys/dev/uart/uart_dev_ns8250.c projects/release-pkg/usr.sbin/ypldap/yp.c projects/release-pkg/usr.sbin/ypldap/ypldap.conf.5 Directory Properties: projects/release-pkg/ (props changed) projects/release-pkg/lib/libc/ (props changed) projects/release-pkg/share/ (props changed) projects/release-pkg/share/man/man4/ (props changed) projects/release-pkg/sys/ (props changed) projects/release-pkg/sys/boot/ (props changed) Modified: projects/release-pkg/UPDATING ============================================================================== --- projects/release-pkg/UPDATING Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/UPDATING Wed Jan 13 04:11:04 2016 (r293803) @@ -31,6 +31,11 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11 disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20160113: + With the addition of ypldap(8), a new _ypldap user is now required + during installworld. "mergemaster -p" can be used to add the user + prior to installworld, as documented in the handbook. + 20151216: The tftp loader (pxeboot) now uses the option root-path directive. As a consequence it no longer looks for a pxeboot.4th file on the tftp Modified: projects/release-pkg/etc/master.passwd ============================================================================== --- projects/release-pkg/etc/master.passwd Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/etc/master.passwd Wed Jan 13 04:11:04 2016 (r293803) @@ -22,5 +22,6 @@ uucp:*:66:66::0:0:UUCP pseudo-user:/var/ pop:*:68:6::0:0:Post Office Owner:/nonexistent:/usr/sbin/nologin auditdistd:*:78:77::0:0:Auditdistd unprivileged user:/var/empty:/usr/sbin/nologin www:*:80:80::0:0:World Wide Web Owner:/nonexistent:/usr/sbin/nologin +_ypldap:*:93:93::0:0:YP Ldap unprivileged user:/var/empty:/usr/sbin/nologin hast:*:845:845::0:0:HAST unprivileged user:/var/empty:/usr/sbin/nologin nobody:*:65534:65534::0:0:Unprivileged user:/nonexistent:/usr/sbin/nologin Modified: projects/release-pkg/lib/libc/sys/futimens.c ============================================================================== --- projects/release-pkg/lib/libc/sys/futimens.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/lib/libc/sys/futimens.c Wed Jan 13 04:11:04 2016 (r293803) @@ -42,8 +42,11 @@ futimens(int fd, const struct timespec t { struct timeval now, tv[2], *tvp; struct stat sb; + int osreldate; - if (__getosreldate() >= 1100056) + osreldate = __getosreldate(); + if (osreldate >= 1100056 || + (osreldate >= 1002506 && osreldate < 1100000)) return (__sys_futimens(fd, times)); if (times == NULL || (times[0].tv_nsec == UTIME_NOW && Modified: projects/release-pkg/lib/libc/sys/utimensat.2 ============================================================================== --- projects/release-pkg/lib/libc/sys/utimensat.2 Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/lib/libc/sys/utimensat.2 Wed Jan 13 04:11:04 2016 (r293803) @@ -31,7 +31,7 @@ .\" @(#)utimes.2 8.1 (Berkeley) 6/4/93 .\" $FreeBSD$ .\" -.Dd January 23, 2015 +.Dd January 12, 2016 .Dt UTIMENSAT 2 .Os .Sh NAME @@ -289,4 +289,4 @@ The and .Fn utimensat system calls appeared in -.Fx 11.0 . +.Fx 10.3 . Modified: projects/release-pkg/lib/libc/sys/utimensat.c ============================================================================== --- projects/release-pkg/lib/libc/sys/utimensat.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/lib/libc/sys/utimensat.c Wed Jan 13 04:11:04 2016 (r293803) @@ -42,8 +42,11 @@ utimensat(int fd, const char *path, cons { struct timeval now, tv[2], *tvp; struct stat sb; + int osreldate; - if (__getosreldate() >= 1100056) + osreldate = __getosreldate(); + if (osreldate >= 1100056 || + (osreldate >= 1002506 && osreldate < 1100000)) return (__sys_utimensat(fd, path, times, flag)); if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0) { Modified: projects/release-pkg/share/man/man4/uart.4 ============================================================================== --- projects/release-pkg/share/man/man4/uart.4 Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/share/man/man4/uart.4 Wed Jan 13 04:11:04 2016 (r293803) @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd August 10, 2015 +.Dd December 9, 2015 .Dt UART 4 .Os .Sh NAME @@ -160,7 +160,9 @@ The API, accessed via is available on the tty device. To use the PPS capture feature with .Xr ntpd 8 , -symlink the tty device to +symlink the tty callout device +.Va /dev/cuau? +to .Va /dev/pps0. .Pp The @@ -175,15 +177,54 @@ it can be set in .Xr loader.conf 5 or .Xr sysctl.conf 5 . +.Pp The following capture modes are available: .Bl -tag -compact -offset "mmmm" -width "mmmm" -.It 0 +.It 0x00 Capture disabled. -.It 1 +.It 0x01 Capture pulses on the CTS line. -.It 2 -Capture pulses on the DCD line (default). +.It 0x02 +Capture pulses on the DCD line. .El +.Pp +The following values may be ORed with the capture mode to configure +capture processing options: +.Bl -tag -compact -offset "mmmm" -width "mmmm" +.It 0x10 +Invert the pulse (RS-232 logic low = ASSERT, high = CLEAR). +.It 0x20 +Attempt to capture narrow pulses. +.El +.Pp +Add the narrow pulse option when the incoming PPS pulse width is small +enough to prevent reliable capture in normal mode. +In narrow mode the driver uses the hardware's ability to latch a line +state change; not all hardware has this capability. +The hardware latch provides a reliable indication that a pulse occurred, +but prevents distinguishing between the CLEAR and ASSERT edges of the pulse. +For each detected pulse, the driver synthesizes both an ASSERT and a CLEAR +event, using the same timestamp for each. +To prevent spurious events when the hardware is intermittently able to +see both edges of a pulse, the driver will not generate a new pair of +events within a half second of the prior pair. +Both normal and narrow pulse modes work with +.Xr ntpd 8 . +.Pp +Add the invert option when the connection to the uart device uses TTL +level signals, or when the PPS source emits inverted pulses. +RFC 2783 defines an ASSERT event as a higher-voltage line level, and a CLEAR +event as a lower-voltage line level, in the context of the RS-232 protocol. +The modem control signals on a TTL-level connection are typically +inverted from the RS-232 levels. +For example, carrier presence is indicated by a high signal on an RS-232 +DCD line, and by a low signal on a TTL DCD line. +This is due to the use of inverting line driver buffers to convert between +TTL and RS-232 line levels in most hardware designs. +Generally speaking, a connection to a DB-9 style connector is an RS-232 +level signal at up to 12 volts. +A connection to header pins or an edge-connector on an embedded board +is typically a TTL signal at 3.3 or 5 volts. .Sh FILES .Bl -tag -width ".Pa /dev/ttyu?.init" -compact .It Pa /dev/ttyu? Modified: projects/release-pkg/sys/arm/arm/pmap-v6-new.c ============================================================================== --- projects/release-pkg/sys/arm/arm/pmap-v6-new.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/arm/arm/pmap-v6-new.c Wed Jan 13 04:11:04 2016 (r293803) @@ -1109,7 +1109,7 @@ pmap_bootstrap(vm_offset_t firstaddr) * mapping of pages. */ #define SYSMAP(c, p, v, n) do { \ - v = (c)pmap_preboot_reserve_pages(1); \ + v = (c)pmap_preboot_reserve_pages(n); \ p = pt2map_entry((vm_offset_t)v); \ } while (0) Modified: projects/release-pkg/sys/boot/efi/libefi/libefi.c ============================================================================== --- projects/release-pkg/sys/boot/efi/libefi/libefi.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/boot/efi/libefi/libefi.c Wed Jan 13 04:11:04 2016 (r293803) @@ -179,7 +179,7 @@ efi_main(EFI_HANDLE image_handle, EFI_SY argv = malloc((argc + 1) * sizeof(CHAR16*)); argc = 0; if (addprog) - argv[argc++] = (CHAR16 *)"loader.efi"; + argv[argc++] = (CHAR16 *)L"loader.efi"; argp = args; while (argp != NULL && *argp != 0) { argp = arg_skipsep(argp); Modified: projects/release-pkg/sys/boot/uboot/lib/copy.c ============================================================================== --- projects/release-pkg/sys/boot/uboot/lib/copy.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/boot/uboot/lib/copy.c Wed Jan 13 04:11:04 2016 (r293803) @@ -100,7 +100,7 @@ uboot_loadaddr(u_int type, void *data, u biggest_block = 0; biggest_size = 0; - subldr = rounddown2((uint64_t)(uintptr_t)_start, KERN_ALIGN); + subldr = rounddown2((uintptr_t)_start, KERN_ALIGN); eubldr = roundup2((uint64_t)uboot_heap_end, KERN_ALIGN); for (i = 0; i < si->mr_no; i++) { if (si->mr[i].flags != MR_ATTR_DRAM) Modified: projects/release-pkg/sys/dev/sfxge/common/efx.h ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx.h Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx.h Wed Jan 13 04:11:04 2016 (r293803) @@ -505,13 +505,6 @@ efx_mac_fcntl_get( __out unsigned int *fcntl_wantedp, __out unsigned int *fcntl_linkp); -#define EFX_MAC_HASH_BITS (1 << 8) - -extern __checkReturn efx_rc_t -efx_mac_hash_set( - __in efx_nic_t *enp, - __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); - #if EFSYS_OPT_MAC_STATS @@ -1923,8 +1916,6 @@ efx_psuedo_hdr_pkt_length_get( typedef enum efx_rxq_type_e { EFX_RXQ_TYPE_DEFAULT, - EFX_RXQ_TYPE_SPLIT_HEADER, - EFX_RXQ_TYPE_SPLIT_PAYLOAD, EFX_RXQ_TYPE_SCATTER, EFX_RXQ_NTYPES } efx_rxq_type_t; Modified: projects/release-pkg/sys/dev/sfxge/common/efx_check.h ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_check.h Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_check.h Wed Jan 13 04:11:04 2016 (r293803) @@ -61,9 +61,6 @@ /* Decode fatal errors */ #if EFSYS_OPT_DECODE_INTR_FATAL # if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) -# if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) -# error "INTR_FATAL not supported on HUNTINGTON or MEDFORD" -# endif # error "INTR_FATAL requires FALCON or SIENA" # endif #endif /* EFSYS_OPT_DECODE_INTR_FATAL */ @@ -138,9 +135,6 @@ /* Support management controller messages */ #if EFSYS_OPT_MCDI # if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) -# if EFSYS_OPT_FALCON -# error "MCDI not supported on FALCON" -# endif # error "MCDI requires SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_MCDI */ @@ -186,14 +180,14 @@ # endif #endif /* EFSYS_OPT_MON_NULL */ -/* Support Siena monitor */ +/* Obsolete option */ #ifdef EFSYS_OPT_MON_SIENA -# error "MON_SIENA is obsolete use MON_MCDI" +# error "MON_SIENA is obsolete (replaced by MON_MCDI)." #endif /* EFSYS_OPT_MON_SIENA*/ -/* Support Huntington monitor */ +/* Obsolete option */ #ifdef EFSYS_OPT_MON_HUNTINGTON -# error "MON_HUNTINGTON is obsolete use MON_MCDI" +# error "MON_HUNTINGTON is obsolete (replaced by MON_MCDI)." #endif /* EFSYS_OPT_MON_HUNTINGTON*/ /* Support monitor statistics (voltage/temperature) */ @@ -265,9 +259,9 @@ # endif #endif /* EFSYS_OPT_PCIE_TUNE */ -/* Support PHY BIST diagnostics */ +/* Obsolete option */ #if EFSYS_OPT_PHY_BIST -# error "PHY_BIST is obsolete. It has been replaced by the BIST option." +# error "PHY_BIST is obsolete (replaced by BIST)." #endif /* EFSYS_OPT_PHY_BIST */ /* Support PHY flags */ @@ -379,7 +373,7 @@ /* Obsolete option */ #ifdef EFSYS_OPT_STAT_NAME -# error "EFSYS_OPT_STAT_NAME is obsolete (replaced by EFSYS_OPT_NAMES)." +# error "STAT_NAME is obsolete (replaced by NAMES)." #endif /* Support PCI Vital Product Data (VPD) */ @@ -399,7 +393,7 @@ /* Obsolete option */ #ifdef EFSYS_OPT_MCAST_FILTER_LIST -# error "MCAST_FILTER_LIST is obsolete and not supported" +# error "MCAST_FILTER_LIST is obsolete and is not supported" #endif /* EFSYS_OPT_MCAST_FILTER_LIST */ /* Support BIST */ Modified: projects/release-pkg/sys/dev/sfxge/common/efx_filter.c ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_filter.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_filter.c Wed Jan 13 04:11:04 2016 (r293803) @@ -97,17 +97,17 @@ static efx_filter_ops_t __efx_filter_sie }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON -static efx_filter_ops_t __efx_filter_hunt_ops = { - hunt_filter_init, /* efo_init */ - hunt_filter_fini, /* efo_fini */ - hunt_filter_restore, /* efo_restore */ - hunt_filter_add, /* efo_add */ - hunt_filter_delete, /* efo_delete */ - hunt_filter_supported_filters, /* efo_supported_filters */ - hunt_filter_reconfigure, /* efo_reconfigure */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +static efx_filter_ops_t __efx_filter_ef10_ops = { + ef10_filter_init, /* efo_init */ + ef10_filter_fini, /* efo_fini */ + ef10_filter_restore, /* efo_restore */ + ef10_filter_add, /* efo_add */ + ef10_filter_delete, /* efo_delete */ + ef10_filter_supported_filters, /* efo_supported_filters */ + ef10_filter_reconfigure, /* efo_reconfigure */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ __checkReturn efx_rc_t efx_filter_insert( @@ -189,10 +189,16 @@ efx_filter_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - efop = (efx_filter_ops_t *)&__efx_filter_hunt_ops; + efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; Modified: projects/release-pkg/sys/dev/sfxge/common/efx_impl.h ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_impl.h Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_impl.h Wed Jan 13 04:11:04 2016 (r293803) @@ -342,6 +342,10 @@ typedef struct efx_intr_ops_s { void (*eio_disable)(efx_nic_t *); void (*eio_disable_unlocked)(efx_nic_t *); efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); + void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); + void (*eio_status_message)(efx_nic_t *, unsigned int, + boolean_t *); + void (*eio_fatal)(efx_nic_t *); void (*eio_fini)(efx_nic_t *); } efx_intr_ops_t; @@ -436,9 +440,9 @@ typedef struct efx_filter_s { #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA falconsiena_filter_t *ef_falconsiena_filter; #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON - hunt_filter_table_t *ef_hunt_filter_table; -#endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + ef10_filter_table_t *ef_ef10_filter_table; +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ } efx_filter_t; extern void Modified: projects/release-pkg/sys/dev/sfxge/common/efx_intr.c ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_intr.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_intr.c Wed Jan 13 04:11:04 2016 (r293803) @@ -67,15 +67,27 @@ static void falconsiena_intr_fini( __in efx_nic_t *enp); +static void +falconsiena_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp); -static __checkReturn boolean_t -falconsiena_intr_check_fatal( - __in efx_nic_t *enp); +static void +falconsiena_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp); static void falconsiena_intr_fatal( __in efx_nic_t *enp); +static __checkReturn boolean_t +falconsiena_intr_check_fatal( + __in efx_nic_t *enp); + + #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ @@ -86,6 +98,9 @@ static efx_intr_ops_t __efx_intr_falcon_ falconsiena_intr_disable, /* eio_disable */ falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_status_line, /* eio_status_line */ + falconsiena_intr_status_message, /* eio_status_message */ + falconsiena_intr_fatal, /* eio_fatal */ falconsiena_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_FALCON */ @@ -97,6 +112,9 @@ static efx_intr_ops_t __efx_intr_siena_o falconsiena_intr_disable, /* eio_disable */ falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_status_line, /* eio_status_line */ + falconsiena_intr_status_message, /* eio_status_message */ + falconsiena_intr_fatal, /* eio_fatal */ falconsiena_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_SIENA */ @@ -108,6 +126,9 @@ static efx_intr_ops_t __efx_intr_ef10_op ef10_intr_disable, /* eio_disable */ ef10_intr_disable_unlocked, /* eio_disable_unlocked */ ef10_intr_trigger, /* eio_trigger */ + ef10_intr_status_line, /* eio_status_line */ + ef10_intr_status_message, /* eio_status_message */ + ef10_intr_fatal, /* eio_fatal */ ef10_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ @@ -261,35 +282,12 @@ efx_intr_status_line( __out uint32_t *qmaskp) { efx_intr_t *eip = &(enp->en_intr); - efx_dword_t dword; + efx_intr_ops_t *eiop = eip->ei_eiop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - /* Ensure Huntington and Falcon/Siena ISR at same location */ - EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST == - ER_DZ_BIU_INT_ISR_REG_OFST); - - /* - * Read the queue mask and implicitly acknowledge the - * interrupt. - */ - EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); - *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); - - EFSYS_PROBE1(qmask, uint32_t, *qmaskp); - -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - *fatalp = B_FALSE; - return; - } -#endif - if (*qmaskp & (1U << eip->ei_level)) - *fatalp = falconsiena_intr_check_fatal(enp); - else - *fatalp = B_FALSE; + eiop->eio_status_line(enp, fatalp, qmaskp); } void @@ -299,39 +297,25 @@ efx_intr_status_message( __out boolean_t *fatalp) { efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - *fatalp = B_FALSE; - return; - } -#endif - if (message == eip->ei_level) - *fatalp = falconsiena_intr_check_fatal(enp); - else - *fatalp = B_FALSE; + eiop->eio_status_message(enp, message, fatalp); } void efx_intr_fatal( __in efx_nic_t *enp) { + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - return; - } -#endif -#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA - falconsiena_intr_fatal(enp); -#endif + eiop->eio_fatal(enp); } @@ -514,6 +498,51 @@ falconsiena_intr_check_fatal( return (B_FALSE); } +static void +falconsiena_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_dword_t dword; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + /* + * Read the queue mask and implicitly acknowledge the + * interrupt. + */ + EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); + *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + EFSYS_PROBE1(qmask, uint32_t, *qmaskp); + + if (*qmaskp & (1U << eip->ei_level)) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + +static void +falconsiena_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp) +{ + efx_intr_t *eip = &(enp->en_intr); + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + if (message == eip->ei_level) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + + static void falconsiena_intr_fatal( __in efx_nic_t *enp) Modified: projects/release-pkg/sys/dev/sfxge/common/efx_mac.c ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_mac.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_mac.c Wed Jan 13 04:11:04 2016 (r293803) @@ -462,55 +462,6 @@ efx_mac_fcntl_get( *fcntl_wantedp = wanted; } -/* - * FIXME: efx_mac_hash_set() should be deleted once all its callers have been - * updated to use efx_mac_multicast_list_set(). - * Then efx_port_t.ep_multicst_hash could be made Falcon/Siena specific as - * well. - */ - __checkReturn efx_rc_t -efx_mac_hash_set( - __in efx_nic_t *enp, - __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket) -{ - efx_port_t *epp = &(enp->en_port); - efx_mac_ops_t *emop = epp->ep_emop; - efx_oword_t old_hash[2]; - unsigned int index; - efx_rc_t rc; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - - memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash)); - - /* Set the lower 128 bits of the hash */ - EFX_ZERO_OWORD(epp->ep_multicst_hash[0]); - for (index = 0; index < 128; index++) { - if (bucket[index] != 0) - EFX_SET_OWORD_BIT(epp->ep_multicst_hash[0], index); - } - - /* Set the upper 128 bits of the hash */ - EFX_ZERO_OWORD(epp->ep_multicst_hash[1]); - for (index = 0; index < 128; index++) { - if (bucket[index + 128] != 0) - EFX_SET_OWORD_BIT(epp->ep_multicst_hash[1], index); - } - - if ((rc = emop->emo_reconfigure(enp)) != 0) - goto fail1; - - return (0); - -fail1: - EFSYS_PROBE1(fail1, efx_rc_t, rc); - - memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash)); - - return (rc); -} - __checkReturn efx_rc_t efx_mac_multicast_list_set( __in efx_nic_t *enp, @@ -912,6 +863,8 @@ fail1: #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA +#define EFX_MAC_HASH_BITS (1 << 8) + /* Compute the multicast hash as used on Falcon and Siena. */ static void falconsiena_mac_multicast_hash_compute( Modified: projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.c ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.c Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.c Wed Jan 13 04:11:04 2016 (r293803) @@ -643,7 +643,6 @@ efx_mcdi_ev_cpl( efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - efx_nic_cfg_t *encp = &enp->en_nic_cfg; efx_mcdi_req_t *emrp; int state; @@ -668,7 +667,7 @@ efx_mcdi_ev_cpl( emip->emi_pending_req = NULL; EFSYS_UNLOCK(enp->en_eslp, state); - if (encp->enc_mcdi_max_payload_length > MCDI_CTL_SDU_LEN_MAX_V1) { + if (emip->emi_max_version >= 2) { /* MCDIv2 response details do not fit into an event. */ efx_mcdi_read_response_header(enp, emrp); } else { Modified: projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.h ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.h Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_mcdi.h Wed Jan 13 04:11:04 2016 (r293803) @@ -69,6 +69,7 @@ struct efx_mcdi_req_s { typedef struct efx_mcdi_iface_s { unsigned int emi_port; + unsigned int emi_max_version; unsigned int emi_seq; efx_mcdi_req_t *emi_pending_req; boolean_t emi_ev_cpl; Modified: projects/release-pkg/sys/dev/sfxge/common/efx_regs_mcdi.h ============================================================================== --- projects/release-pkg/sys/dev/sfxge/common/efx_regs_mcdi.h Wed Jan 13 01:50:02 2016 (r293802) +++ projects/release-pkg/sys/dev/sfxge/common/efx_regs_mcdi.h Wed Jan 13 04:11:04 2016 (r293803) @@ -299,6 +299,9 @@ * have already installed filters. See the comment at * MC_CMD_WORKAROUND_BUG26807. */ #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 +/* The clock whose frequency you've attempted to set set + * doesn't exist on this NIC */ +#define MC_CMD_ERR_NO_CLOCK 0x1015 #define MC_CMD_ERR_CODE_OFST 0 @@ -318,9 +321,11 @@ /* Point to the copycode entry point. */ #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) +#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) /* Points to the recovery mode entry point. */ #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) +#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) /* The command set exported by the boot ROM (MCDI v0) */ #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ @@ -1456,9 +1461,11 @@ #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ -#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8 +#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ +/* Clear previous test result and prepare for restarting DDR test */ +#define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 @@ -1475,6 +1482,10 @@ #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum: Get the BSP version */ #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 +/* enum: Get build register for V2 (SFA974X) */ +#define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 +/* enum: GEt the services register for V2 (SFA974X) */ +#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 /* MC_CMD_FC_IN_READ_MAP msgrequest */ #define MC_CMD_FC_IN_READ_MAP_LEN 8 @@ -1832,6 +1843,7 @@ #define MC_CMD_FC_IN_DDR_OP_OFST 4 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ +#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_OFST 8 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ @@ -1855,6 +1867,15 @@ /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 +/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ +#define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 +/* MC_CMD_FC_IN_CMD_OFST 0 */ +/* MC_CMD_FC_IN_DDR_OP_OFST 4 */ +/* Affected bank */ +/* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ +/* Size of DDR */ +#define MC_CMD_FC_IN_DDR_SIZE_OFST 12 + /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ @@ -2387,6 +2408,116 @@ #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 +/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 +#define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 +/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ +/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 + /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 @@ -2437,6 +2568,40 @@ #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 +/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 +/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ +/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 + /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 /* Qsys system ID */ @@ -2718,6 +2883,9 @@ /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 +/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ +#define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 + /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 @@ -3131,6 +3299,8 @@ #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 /* FPGA type - read from CPLD straps */ #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ /* FPGA state (debug) */ #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 /* FPGA image - partition from which loaded */ @@ -3144,23 +3314,28 @@ /* Random pieces of information */ #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ -#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 +#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum: CPLD apparently good */ -#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 +#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum: FPGA working normally */ -#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 +#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum: FPGA is powered */ -#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 +#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum: Board has incompatible SODIMMs fitted */ -#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 +#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum: Board has ByteBlaster connected */ -#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 -/* Revision of Modena board */ +#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 +/* enum: FPGA Boot flash has an invalid header. */ +#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 +/* enum: FPGA Application flash is accessible. */ +#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 +/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ /* Result of FC booting - not valid while a ByteBlaster is connected. */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 /* enum: No error */ @@ -3931,15 +4106,30 @@ /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 -/* Uncorrected error on transmit timestamps in NIC clock format */ +/* Uncorrected error on PTP transmit timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 -/* Uncorrected error on receive timestamps in NIC clock format */ +/* Uncorrected error on PTP receive timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 /* Uncorrected error on PPS output in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 /* Uncorrected error on PPS input in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 +/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 +/* Uncorrected error on PTP transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 +/* Uncorrected error on PTP receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 +/* Uncorrected error on PPS output in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 +/* Uncorrected error on PPS input in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 +/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 +/* Uncorrected error on non-PTP receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 + /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 /* Results of testing */ @@ -5203,7 +5393,7 @@ #define MC_CMD_SET_MAC 0x2c #undef MC_CMD_0x2c_PRIVILEGE_CTG -#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK +#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL /* MC_CMD_SET_MAC_IN msgrequest */ #define MC_CMD_SET_MAC_IN_LEN 28 @@ -5950,6 +6140,37 @@ /* amount to read in bytes */ #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 +/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ +#define MC_CMD_NVRAM_READ_IN_V2_LEN 16 +#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ +#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 +/* amount to read in bytes */ +#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 +/* Optional control info. If a partition is stored with an A/B versioning + * scheme (i.e. in more than one physical partition in NVRAM) the host can set + * this to control which underlying physical partition is used to read data + * from. This allows it to perform a read-modify-write-verify with the write + * lock continuously held by calling NVRAM_UPDATE_START, reading the old + * contents using MODE=TARGET_CURRENT, overwriting the old partition and then + * verifying by reading with MODE=TARGET_BACKUP. + */ +#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 +/* enum: Same as omitting MODE: caller sees data in current partition unless it + * holds the write lock in which case it sees data in the partition it is + * updating. *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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