From owner-svn-src-stable@FreeBSD.ORG Tue Nov 16 20:21:54 2010 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 5FFE11065698; Tue, 16 Nov 2010 20:21:54 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 339888FC31; Tue, 16 Nov 2010 20:21:54 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oAGKLs1l066203; Tue, 16 Nov 2010 20:21:54 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oAGKLsNg066201; Tue, 16 Nov 2010 20:21:54 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201011162021.oAGKLsNg066201@svn.freebsd.org> From: Pyun YongHyeon Date: Tue, 16 Nov 2010 20:21:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r215403 - stable/8/sys/dev/re X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Nov 2010 20:21:54 -0000 Author: yongari Date: Tue Nov 16 20:21:53 2010 New Revision: 215403 URL: http://svn.freebsd.org/changeset/base/215403 Log: MFC r214992: Reduce spin wait time consumed in GMII register access routine. There were a couple of attempts in the past to reduce it since it took more than 1ms. Because mii_tick() periodically polls link status, waiting more than 1ms for each GMII register access was overkill. Unfortunately all previous attempts were failed with various ways on different controllers. This time, add additional 20us dealy at the end of GMII register access which seems to requirement of all RealTek controllers to issue next GMII register access request. This is the same way what Linux does. Modified: stable/8/sys/dev/re/if_re.c Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/dev/re/if_re.c ============================================================================== --- stable/8/sys/dev/re/if_re.c Tue Nov 16 17:44:09 2010 (r215402) +++ stable/8/sys/dev/re/if_re.c Tue Nov 16 20:21:53 2010 (r215403) @@ -423,13 +423,12 @@ re_gmii_readreg(device_t dev, int phy, i } CSR_WRITE_4(sc, RL_PHYAR, reg << 16); - DELAY(1000); for (i = 0; i < RL_PHY_TIMEOUT; i++) { rval = CSR_READ_4(sc, RL_PHYAR); if (rval & RL_PHYAR_BUSY) break; - DELAY(100); + DELAY(25); } if (i == RL_PHY_TIMEOUT) { @@ -437,6 +436,11 @@ re_gmii_readreg(device_t dev, int phy, i return (0); } + /* + * Controller requires a 20us delay to process next MDIO request. + */ + DELAY(20); + return (rval & RL_PHYAR_PHYDATA); } @@ -451,13 +455,12 @@ re_gmii_writereg(device_t dev, int phy, CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); - DELAY(1000); for (i = 0; i < RL_PHY_TIMEOUT; i++) { rval = CSR_READ_4(sc, RL_PHYAR); if (!(rval & RL_PHYAR_BUSY)) break; - DELAY(100); + DELAY(25); } if (i == RL_PHY_TIMEOUT) { @@ -465,6 +468,11 @@ re_gmii_writereg(device_t dev, int phy, return (0); } + /* + * Controller requires a 20us delay to process next MDIO request. + */ + DELAY(20); + return (0); }