From nobody Mon Apr 4 11:06:07 2022 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 082541A97262; Mon, 4 Apr 2022 11:06:08 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4KX7Hg3JF1z3NfR; Mon, 4 Apr 2022 11:06:07 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1649070367; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=trxWIRTdQk8ZyW6caUjy1dEP/EmXYtNQGAB3PI2Dv78=; b=ZADZ/2o0qqmpkq4UgfyLYwfDBaUAhbU0NtiI6o3P94f8GSa0r+THsj08/G97l7ezWpViBZ f0Dozqh1RCmOmPiaHvg+CEP45wedv/adadMntSZW/s+7kWP0E/QHHJ4mseU7heOYJeyyIQ GX6IUTnSICNg9vo/ku4hUAVH/mafcTwclwYFfcXQ7KrggUfp/np037Bel8AUBt+/PqcvJI BtMraiYBBmqGj3YnwhVDTsx9NCSWij6lbk82ffPnnzTiT3ohx50nFIIvMkoXTZoohSCpP5 oxgGXTCBT23LFCEsmn4fWYYcdPj+lVfOXVRbqqmn6uSvRe7Oe7NHuWZKX6J74Q== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 31A3B10C9C; Mon, 4 Apr 2022 11:06:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 234B67qZ086644; Mon, 4 Apr 2022 11:06:07 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 234B67Fo086643; Mon, 4 Apr 2022 11:06:07 GMT (envelope-from git) Date: Mon, 4 Apr 2022 11:06:07 GMT Message-Id: <202204041106.234B67Fo086643@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: 9705371ada9b - stable/13 - Correct the location of the arm64 PMCR register List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 9705371ada9b78bf314a8217c51b58270d55a472 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1649070367; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=trxWIRTdQk8ZyW6caUjy1dEP/EmXYtNQGAB3PI2Dv78=; b=ekh/Mk5U+JMu0+fYA/XRox9HymPO6G+aPjKu77NMZjQMBVZ7QGl45SjbtRempmPdIn7SJh ElRePp16aEf4vQAnms/N0Eh/x/hRRJxKKDoXZZGLO04Wp0FuS0LkPp5pYHd+4gXVnnuoFO Bmuy4WzpzL00TxCNPv4n40JV1tBtOvjFDknbDlzcBjedmJMspyCFsggjJo0N5cxarkEWA5 zXqWMbIG/fa+BhFcvap6Dy+fVoNvlAubwfk4b262Rq+8NrSf0OqeDNGCLidW+7n8xbC7in +bsa47hvvcVG6aoVJHIElUhovvA4K2aVH2nY2DTxW5kC0hN3GJ6pEgjm/IhBBw== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1649070367; a=rsa-sha256; cv=none; b=MJ2E3J7ZGX7y1LqkEeXK7jVtqnitj9kj7Y542PVwAC9l2DLQS4qNRwLJA9kRZK65WUCtn/ TUvIZSyom7Krlp2blsu8akJJ7slYcfb8VUVV+koaptL3t9SafFjFjZLccRD8mMbSGUAddn Eu6kxxkVQmfKD0YD/2WTt4i/vWumkvTFvqJVUNkHxddK6yAvCC7CMW8ZVCelCWmBHo8no5 YZ1R4Tyx7/9CpuOnkaz6SXopdgfajlkogpQnpHgk2vK5x5T6D6YCeovvDP9OpHcYFl3oM0 umSVPNO3JRmB+lzfivzHzNw7JOLaZkSJr/JgprANCfa4mdJMXkQ20tnpjOQIvA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=9705371ada9b78bf314a8217c51b58270d55a472 commit 9705371ada9b78bf314a8217c51b58270d55a472 Author: Andrew Turner AuthorDate: 2022-03-11 10:56:42 +0000 Commit: Andrew Turner CommitDate: 2022-04-04 09:37:07 +0000 Correct the location of the arm64 PMCR register This was one of the last registers to not be in alphabetical order in armreg.h. Fix this to make it easier to find. Sponsored by: Innovate UK (cherry picked from commit a1b4e4fa9a2f8bef9adff9e93cc5152e46a2ff4e) --- sys/arm64/include/armreg.h | 55 +++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 3a26c7bb5d40..dcaab1375bf8 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -968,6 +968,33 @@ #define PMBSR_EC_SHIFT 26 #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) +/* PMCR_EL0 - Perfomance Monitoring Counters */ +#define PMCR_E (1 << 0) /* Enable all counters */ +#define PMCR_P (1 << 1) /* Reset all counters */ +#define PMCR_C (1 << 2) /* Clock counter reset */ +#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ +#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ +#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define PMCR_LC (1 << 6) /* Long cycle count enable */ +#define PMCR_IMP_SHIFT 24 /* Implementer code */ +#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) +#define PMCR_IMP_ARM 0x41 +#define PMCR_IDCODE_SHIFT 16 /* Identification code */ +#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) +#define PMCR_IDCODE_CORTEX_A57 0x01 +#define PMCR_IDCODE_CORTEX_A72 0x02 +#define PMCR_IDCODE_CORTEX_A53 0x03 +#define PMCR_IDCODE_CORTEX_A73 0x04 +#define PMCR_IDCODE_CORTEX_A35 0x0a +#define PMCR_IDCODE_CORTEX_A76 0x0b +#define PMCR_IDCODE_NEOVERSE_N1 0x0c +#define PMCR_IDCODE_CORTEX_A77 0x10 +#define PMCR_IDCODE_CORTEX_A55 0x45 +#define PMCR_IDCODE_NEOVERSE_E1 0x46 +#define PMCR_IDCODE_CORTEX_A75 0x4a +#define PMCR_N_SHIFT 11 /* Number of counters implemented */ +#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) + /* PMSCR_EL1 */ #define PMSCR_EL1 MRS_REG(PMSCR_EL1) #define PMSCR_EL1_op0 0x3 @@ -1433,32 +1460,4 @@ #define TTBR_CnP_SHIFT 0 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) - -/* Perfomance Monitoring Counters */ -#define PMCR_E (1 << 0) /* Enable all counters */ -#define PMCR_P (1 << 1) /* Reset all counters */ -#define PMCR_C (1 << 2) /* Clock counter reset */ -#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ -#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ -#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define PMCR_LC (1 << 6) /* Long cycle count enable */ -#define PMCR_IMP_SHIFT 24 /* Implementer code */ -#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) -#define PMCR_IMP_ARM 0x41 -#define PMCR_IDCODE_SHIFT 16 /* Identification code */ -#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) -#define PMCR_IDCODE_CORTEX_A57 0x01 -#define PMCR_IDCODE_CORTEX_A72 0x02 -#define PMCR_IDCODE_CORTEX_A53 0x03 -#define PMCR_IDCODE_CORTEX_A73 0x04 -#define PMCR_IDCODE_CORTEX_A35 0x0a -#define PMCR_IDCODE_CORTEX_A76 0x0b -#define PMCR_IDCODE_NEOVERSE_N1 0x0c -#define PMCR_IDCODE_CORTEX_A77 0x10 -#define PMCR_IDCODE_CORTEX_A55 0x45 -#define PMCR_IDCODE_NEOVERSE_E1 0x46 -#define PMCR_IDCODE_CORTEX_A75 0x4a -#define PMCR_N_SHIFT 11 /* Number of counters implemented */ -#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) - #endif /* !_MACHINE_ARMREG_H_ */