From owner-svn-src-head@FreeBSD.ORG Mon Apr 22 08:28:54 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 34FDBC92; Mon, 22 Apr 2013 08:28:54 +0000 (UTC) (envelope-from dmarion@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 2757B172F; Mon, 22 Apr 2013 08:28:54 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.6/8.14.6) with ESMTP id r3M8SrZp063331; Mon, 22 Apr 2013 08:28:53 GMT (envelope-from dmarion@svn.freebsd.org) Received: (from dmarion@localhost) by svn.freebsd.org (8.14.6/8.14.5/Submit) id r3M8SrUc063330; Mon, 22 Apr 2013 08:28:53 GMT (envelope-from dmarion@svn.freebsd.org) Message-Id: <201304220828.r3M8SrUc063330@svn.freebsd.org> From: Damjan Marion Date: Mon, 22 Apr 2013 08:28:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r249762 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Apr 2013 08:28:54 -0000 Author: dmarion Date: Mon Apr 22 08:28:53 2013 New Revision: 249762 URL: http://svnweb.freebsd.org/changeset/base/249762 Log: Initialize GIC_PMRR register on ARM GIC. Provided by: Thomas Skibo Modified: head/sys/arm/arm/gic.c Modified: head/sys/arm/arm/gic.c ============================================================================== --- head/sys/arm/arm/gic.c Mon Apr 22 06:47:27 2013 (r249761) +++ head/sys/arm/arm/gic.c Mon Apr 22 08:28:53 2013 (r249762) @@ -134,6 +134,9 @@ gic_init_secondary(void) /* Enable CPU interface */ gic_c_write_4(GICC_CTLR, 1); + /* Set priority mask register. */ + gic_c_write_4(GICC_PMR, 0xff); + /* Enable interrupt distribution */ gic_d_write_4(GICD_CTLR, 0x01); @@ -199,6 +202,9 @@ arm_gic_attach(device_t dev) /* Enable CPU interface */ gic_c_write_4(GICC_CTLR, 1); + /* Set priority mask register. */ + gic_c_write_4(GICC_PMR, 0xff); + /* Enable interrupt distribution */ gic_d_write_4(GICD_CTLR, 0x01);