From owner-svn-src-head@FreeBSD.ORG Tue Jul 8 10:49:10 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 4C009224; Tue, 8 Jul 2014 10:49:10 +0000 (UTC) Received: from alchemy.franken.de (alchemy.franken.de [194.94.249.214]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "alchemy.franken.de", Issuer "alchemy.franken.de" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id BCEC82463; Tue, 8 Jul 2014 10:49:09 +0000 (UTC) Received: from alchemy.franken.de (localhost [127.0.0.1]) by alchemy.franken.de (8.14.8/8.14.8/ALCHEMY.FRANKEN.DE) with ESMTP id s68An0nW074412 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 8 Jul 2014 12:49:00 +0200 (CEST) (envelope-from marius@alchemy.franken.de) Received: (from marius@localhost) by alchemy.franken.de (8.14.8/8.14.8/Submit) id s68An0gh074411; Tue, 8 Jul 2014 12:49:00 +0200 (CEST) (envelope-from marius) Date: Tue, 8 Jul 2014 12:49:00 +0200 From: Marius Strobl To: Hans Petter Selasky Subject: Re: svn commit: r268354 - head/sys/dev/usb/controller Message-ID: <20140708104900.GG7615@alchemy.franken.de> References: <201407070517.s675HHr9048970@svn.freebsd.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201407070517.s675HHr9048970@svn.freebsd.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.4.3 (alchemy.franken.de [0.0.0.0]); Tue, 08 Jul 2014 12:49:00 +0200 (CEST) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Jul 2014 10:49:10 -0000 On Mon, Jul 07, 2014 at 05:17:17AM +0000, Hans Petter Selasky wrote: > Author: hselasky > Date: Mon Jul 7 05:17:16 2014 > New Revision: 268354 > URL: http://svnweb.freebsd.org/changeset/base/268354 > > Log: > Improve support for Intel Lynx Point USB 3.0 controllers by masking > the port routing bits like done in Linux. > > MFC after: 1 week > Tested by: Tur-Wei Chan > > Modified: > head/sys/dev/usb/controller/xhci_pci.c > head/sys/dev/usb/controller/xhcireg.h > > Modified: head/sys/dev/usb/controller/xhci_pci.c > ============================================================================== > --- head/sys/dev/usb/controller/xhci_pci.c Mon Jul 7 03:10:56 2014 (r268353) > +++ head/sys/dev/usb/controller/xhci_pci.c Mon Jul 7 05:17:16 2014 (r268354) > @@ -157,6 +157,9 @@ xhci_pci_port_route(device_t self, uint3 > temp |= set; > temp &= ~clear; > > + /* Don't set bits which the hardware doesn't support */ > + temp &= pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); > + > pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4); > pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4); > Is there a reason you only exclude ports that PCI_XHCI_INTEL_USB3PRM reports as not switchable to SuperSpeed, but not also ports that the hardware reports as not routable between the EHCI and xHCI controller via PCI_XHCI_INTEL_USB2PRM (as Linux does, which might be wront, though)? > > Modified: head/sys/dev/usb/controller/xhcireg.h > ============================================================================== > --- head/sys/dev/usb/controller/xhcireg.h Mon Jul 7 03:10:56 2014 (r268353) > +++ head/sys/dev/usb/controller/xhcireg.h Mon Jul 7 05:17:16 2014 (r268354) > @@ -35,7 +35,9 @@ > #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ > > #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ > +#define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ > #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ > +#define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ > > /* XHCI capability registers */ > #define XHCI_CAPLENGTH 0x00 /* RO capability */ Marius