From owner-freebsd-mips@FreeBSD.ORG Sat Jul 16 00:30:37 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 79D7F106566B for ; Sat, 16 Jul 2011 00:30:37 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-gx0-f182.google.com (mail-gx0-f182.google.com [209.85.161.182]) by mx1.freebsd.org (Postfix) with ESMTP id 38CFA8FC14 for ; Sat, 16 Jul 2011 00:30:36 +0000 (UTC) Received: by gxk28 with SMTP id 28so911943gxk.13 for ; Fri, 15 Jul 2011 17:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=IZx9YOuPhevCVTqqta5FwreTxXDUf7ttPtGRWCyjd/s=; b=Xpa+HXxtWX9YrSreOAzXvabu4rCtJHadLcZM/I8Zy0SSnnW6KeDqC/2rTUMBL+2oSQ Y/XjN61BGxoI3hkeDBXz9nSXIBAzo44ptfcER3yHgAfLw6TcFTtTJuQNFuccVQlXiIpi xyvh5sSer1hU9Z26KZNGMdxhSgM8SWLhIfFO0= MIME-Version: 1.0 Received: by 10.150.46.4 with SMTP id t4mr3871947ybt.386.1310776235491; Fri, 15 Jul 2011 17:30:35 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.150.197.5 with HTTP; Fri, 15 Jul 2011 17:30:35 -0700 (PDT) In-Reply-To: References: Date: Sat, 16 Jul 2011 08:30:35 +0800 X-Google-Sender-Auth: DEWtqC-_M7p4eLCQtMisdN9i-aY Message-ID: From: Adrian Chadd To: Robert Millan Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] Fix initialization of i8259 controller on MALTA X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jul 2011 00:30:37 -0000 Committed in r224072. Thanks! Adrian On 15 July 2011 08:16, Robert Millan wrote: > Hi, > > i8259 controller is initialized incorrectly on MALTA. =A0It writes mask > bits to control register and control bits to mask register. > > The former causes ICW1_RESET|ICW1_LTIM combination to be written to > control register, which on QEMU results in "level sensitive irq not > supported" error. > > -- > Robert Millan > > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org" > >