Date: Tue, 09 Apr 2019 18:07:47 +0000 From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 236838] Commit r340224 prevents loading the kernel for some Intel Xeon hardware Message-ID: <bug-236838-227-dNn1fGRYAG@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-236838-227@https.bugs.freebsd.org/bugzilla/> References: <bug-236838-227@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D236838 --- Comment #11 from commit-hook@freebsd.org --- A commit references this bug: Author: kib Date: Tue Apr 9 18:07:18 UTC 2019 New revision: 346062 URL: https://svnweb.freebsd.org/changeset/base/346062 Log: pci_cfgreg.c: Use io port config access for early boot time. Some early PCIe chipsets are explicitly listed in the white-list to enable use of the MMIO config space accesses, perhaps because ACPI tables were not reliable source of the base MCFG address at that time. For that chipsets, MCFG base was read from the known chipset MCFGbase config register. During very early stage of boot, when access to the PCI config space is performed (see e.g. pci_early_quirks.c), we cannot map 255MB of registers because the method used with pre-boot pmap overflows initial kernel page tables. Move fallback to read MCFGbase to the attachment method of the x86/legacy device, which removes code duplication, and results in the use of io accesses until MCFG is parsed or legacy attach called. For amd64, pre-initialize cfgmech with CFGMECH_1, right now we dynamically assign CFGMECH_1 to it anyway, and remove checks for CFGMECH_NONE. There is a mention in the Intel documentation for corresponding chipsets that OS must use either io port or MMIO access method, but we already break this rule by reading MCFGbase register, so one more access seems to be innocent. Reported by: longwitz@incore.de PR: 236838 Reviewed by: avg (other version), jhb Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D19833 Changes: head/sys/amd64/pci/pci_cfgreg.c head/sys/i386/pci/pci_cfgreg.c head/sys/x86/include/pci_cfgreg.h head/sys/x86/x86/legacy.c --=20 You are receiving this mail because: You are the assignee for the bug.=
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