From owner-svn-src-all@FreeBSD.ORG Thu May 8 20:02:38 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id E24367CB; Thu, 8 May 2014 20:02:38 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B5DC4D62; Thu, 8 May 2014 20:02:38 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s48K2crm004200; Thu, 8 May 2014 20:02:38 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s48K2cNQ004199; Thu, 8 May 2014 20:02:38 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201405082002.s48K2cNQ004199@svn.freebsd.org> From: Ian Lepore Date: Thu, 8 May 2014 20:02:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r265705 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 May 2014 20:02:39 -0000 Author: ian Date: Thu May 8 20:02:38 2014 New Revision: 265705 URL: http://svnweb.freebsd.org/changeset/base/265705 Log: Consolitate all the AP core startup stuff under a single #ifdef SMP block. Remove some other ifdefs that came in with a copy/paste that mean basically "if this processor supports multicore stuff", because if you're starting up an AP core... it does. Modified: head/sys/arm/arm/locore.S Modified: head/sys/arm/arm/locore.S ============================================================================== --- head/sys/arm/arm/locore.S Thu May 8 19:45:31 2014 (r265704) +++ head/sys/arm/arm/locore.S Thu May 8 20:02:38 2014 (r265705) @@ -308,11 +308,6 @@ Lreal_start: Lend: .word _edata -#ifdef SMP -Lstartup_pagetable_secondary: - .word temp_pagetable -#endif - .Lstart: .word _edata .word _ebss @@ -320,10 +315,6 @@ Lstartup_pagetable_secondary: .Lvirt_done: .word virt_done -#if defined(SMP) -.Lmpvirt_done: - .word mpvirt_done -#endif .Lmainreturned: .asciz "main() returned" @@ -350,6 +341,11 @@ pagetable: #if defined(SMP) +.Lmpvirt_done: + .word mpvirt_done +Lstartup_pagetable_secondary: + .word temp_pagetable + ASENTRY_NP(mpentry) /* Make sure interrupts are disabled. */ @@ -379,26 +375,20 @@ Ltag: bic r0, r0, #0xf0000000 orr r0, r0, #PHYSADDR ldr r0, [r0] -#if defined(SMP) orr r0, r0, #2 /* Set TTB shared memory flag */ -#endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ -#endif /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) orr r0, r0, #CPU_CONTROL_V6_EXTPAGE orr r0, r0, #CPU_CONTROL_AF_ENABLE -#endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) mcr p15, 0, r0, c1, c0, 0 nop @@ -426,7 +416,7 @@ mpvirt_done: /* NOTREACHED */ .Lmpreturned: - .asciz "main() returned" + .asciz "init_secondary() returned" .align 0 END(mpentry) #endif