Date: Sun, 10 Dec 2006 23:42:29 GMT From: Sam Leffler <sam@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 111415 for review Message-ID: <200612102342.kBANgTCf070918@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=111415 Change 111415 by sam@sam_ebb on 2006/12/10 23:42:21 whitespace; maintain prevailing style Affected files ... .. //depot/projects/crypto/sys/dev/hifn/hifn7751reg.h#3 edit Differences ... ==== //depot/projects/crypto/sys/dev/hifn/hifn7751reg.h#3 (text+ko) ==== @@ -118,9 +118,9 @@ #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control -- second mapping */ -#define HIFN_0_MUTE1 0x80 -#define HIFN_0_MUTE2 0x90 +#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ +#define HIFN_0_MUTE1 0x80 +#define HIFN_0_MUTE2 0x90 #define HIFN_0_SPACESIZE 0x100 /* Register space size */ /* Processing Unit Control Register (HIFN_0_PUCTRL) */ @@ -220,7 +220,7 @@ #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ +#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ #define HIFN_1_REVID 0x98 /* Revision ID */ @@ -232,9 +232,9 @@ #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ #define HIFN_1_RNG_DATA 0x318 /* RNG data */ -#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ +#define HIFN_1_PUB_MODE 0x320 /* PK mode */ +#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ +#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ @@ -313,14 +313,14 @@ #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ /* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 +#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ +#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ +#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ +#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ +#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 +#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 +#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 +#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ #define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ @@ -375,11 +375,11 @@ /* Public status register (HIFN_1_PUB_STATUS) */ #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ +#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ +#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ +#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ +#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ +#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ /* Public interrupt enable register (HIFN_1_PUB_IEN) */ #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ @@ -432,8 +432,8 @@ /* * Public Key Engine Mode Register */ -#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ +#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ +#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ /*********************************************************************
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